Search Results - "MOSFET."

1

Understanding MOSFET mismatch for analog design. by Drennan, P.G

Published in IEEE Journal of solid state circuits

Article

2

Simultaneous switching noise analysis using application specific device modeling. by Li Ding

Published in IEEE Transactions on VLSI systems

Article

3

The High-k Solution. by Bohr, M.T

Published in IEEE spectrum

Article

4

The High-k Solution. by Bohr, M.T

Published in IEEE spectrum

Article

5

Effects of uniaxial mechanical stress on drive current of 0.13 μm MOSFETs. by Wang, Y.G

Published in IEEE Transactions on electron devices

Article

6

Implementation of a comprehensive and robust MOSFET model in cadence SPICE for ESD applications. by Gao, X.F

Published in IEEE Transactions on computer-aided design of integrated circuits and systems

Article

7

A multiple-valued logic and memory with combined single-electron and metal-oxide-semiconductor transistors. by Inokawa, H.

Published in IEEE Transactions on electron devices

Article

8

A multiple-valued logic and memory with combined single-electron and metal-oxide-semiconductor transistors. by Inokawa, H.

Published in IEEE Transactions on electron devices

Article

9

GaAsing up cellphones. by Goldstein, H.

Published in IEEE spectrum

Article

10

A CAD methodology for optimizing transistor current and sizing in analog CMOS design. by Binkley, D.M

Published in IEEE Transactions on computer-aided design of integrated circuits and systems

Article

Search Results - "MOSFET."

Understanding MOSFET mismatch for analog design. by Drennan, P.G

Simultaneous switching noise analysis using application specific device modeling. by Li Ding

The High-k Solution. by Bohr, M.T

The High-k Solution. by Bohr, M.T

Effects of uniaxial mechanical stress on drive current of 0.13 μm MOSFETs. by Wang, Y.G

Implementation of a comprehensive and robust MOSFET model in cadence SPICE for ESD applications. by Gao, X.F

A multiple-valued logic and memory with combined single-electron and metal-oxide-semiconductor transistors. by Inokawa, H.

A multiple-valued logic and memory with combined single-electron and metal-oxide-semiconductor transistors. by Inokawa, H.

GaAsing up cellphones. by Goldstein, H.

A CAD methodology for optimizing transistor current and sizing in analog CMOS design. by Binkley, D.M

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