Showing 501 - 510 results of 616 for search '"Levellers."', सवाल का समय: 0.02सेकंड परिणाम को परिष्कृत करें
  1. 501

    Design of wireless on-wafer submicron characterization system. द्वारा Moore, B.

    में प्रकाशित IEEE Transactions on VLSI systems
    लेख

    Design of wireless on-wafer submicron characterization system.
  2. 502

    Static task-scheduling algorithms for battery-powered DVS systems. द्वारा Chowdhury, P.

    में प्रकाशित IEEE Transactions on VLSI systems
    लेख

    Static task-scheduling algorithms for battery-powered DVS systems.
  3. 503

    Efficient algorithms for multilevel power estimation of VLSI circuits. द्वारा Bachmann, W.W

    में प्रकाशित IEEE Transactions on VLSI systems
    लेख

    Efficient algorithms for multilevel power estimation of VLSI circuits.
  4. 504

    A macro-level scheduling method using Lagrangian relaxation. द्वारा Yuanhui Zhang

    में प्रकाशित IEEE Transactions on robotics and automation
    लेख

    A macro-level scheduling method using Lagrangian relaxation.
  5. 505

    Product form solution for generalized stochastic Petri nets. द्वारा Balbo, G.

    में प्रकाशित IEEE Transactions on software engineering
    लेख

    Product form solution for generalized stochastic Petri nets.
  6. 506

    A methodology for architecture-level reliability risk analysis. द्वारा Yacoub, S.M

    में प्रकाशित IEEE Transactions on software engineering
    लेख

    A methodology for architecture-level reliability risk analysis.
  7. 507

    Speech recognition and utterance verification based on a generalized confidence score. द्वारा Myoung-Wan Koo

    में प्रकाशित IEEE Transactions on speech and audio processing
    लेख

    Speech recognition and utterance verification based on a generalized confidence score.
  8. 508

    Overview of a compiler for synthesizing MATLAB programs onto FPGAs. द्वारा Banerjee, P.

    में प्रकाशित IEEE Transactions on VLSI systems
    लेख

    Overview of a compiler for synthesizing MATLAB programs onto FPGAs.
  9. 509

    A jitter characterization system using a component-invariant Vernier delay line. द्वारा Chan, A.H

    में प्रकाशित IEEE Transactions on VLSI systems
    लेख

    A jitter characterization system using a component-invariant Vernier delay line.
  10. 510

    Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect. द्वारा Efthymiou, A.

    में प्रकाशित IEEE Transactions on VLSI systems
    लेख

    Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect.

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