Showing 1 - 7 results of 7 for search '"Leakage power reduction."', query time: 0.02s Refine Results
  1. 1

    Characterization and modeling of run-time techniques for leakage power reduction. by Yuh-Fang Tsai

    Article

    Characterization and modeling of run-time techniques for leakage power reduction.
  2. 2

    A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor. by Khellah, M.

    Article

    A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor.
  3. 3

    A forward body-biased low-leakage SRAM cache device, circuit and architecture considerations. by Kim, C.H

    Article

    A forward body-biased low-leakage SRAM cache device, circuit and architecture considerations.
  4. 4

    Low-power scan design using first-level supply gating. by Bhunia, S.

    Article

    Low-power scan design using first-level supply gating.
  5. 5

    Quantitative analysis and optimization techniques for on-chip cache leakage power. by Nam Sung Kim

    Article

    Quantitative analysis and optimization techniques for on-chip cache leakage power.
  6. 6

    Soft errors issues in low-power caches. by Degalahal, V.

    Article

    Soft errors issues in low-power caches.
  7. 7

    Circuit and microarchitectural techniques for reducing cache leakage power. by Nam Sung Kim

    Article

    Circuit and microarchitectural techniques for reducing cache leakage power.

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