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Impact of interfacial layer and transition region on gate current performance for high-K gate dielectric stack its tradeoff with gate capacitance.
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Yang-Yu Fan
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IEEE Transactions on electron devices
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Fully depleted, back-illuminated charge-coupled devices fabricated on high-resistivity silicon.
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Holland, S.E
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Statistical analysis of subthreshold leakage current for VLSI circuits.
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Rao, R.
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IEEE Transactions on VLSI systems
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Leakage current reduction in CMOS VLSI circuits by input vector control.
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Abdollahi, A.
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Gate oxide leakage current analysis and reduction for VLSI circuits.
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Dongwoo Lee
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LECTOR a technique for leakage reduction in CMOS circuits.
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Hanchate, N.
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DATABASE
Union Catalog (Buklod)
26 results
26
AUTHOR
Abdollahi, A.
1 results
1
Chih-Ju Chou
1 results
1
Chua-Chin Wang
1 results
1
Dejun Han
1 results
1
Dongwoo Lee
1 results
1
Hanchate, N.
1 results
1
Heinrich, C.
1 results
1
Holland, S.E
1 results
1
Inoue, I.
1 results
1
Kanno, Y.
1 results
1
Kursun, V.
1 results
1
Lai, J.-L
1 results
1
Lee, Hong-Sub
1 results
1
Lih, Y.
1 results
1
Loukianova, N.V
1 results
1
Lueftner, T.
1 results
1
Markovic, D.
1 results
1
Ming-Dou Ker
1 results
1
Nieh, R.E
1 results
1
Nomura, M.
1 results
1
Onishi, K.
1 results
1
Rao, R.
1 results
1
Sohn, K.
1 results
1
Takayanagi, I.
1 results
1
Taur, Y.
1 results
1
Yang-Yu Fan
1 results
1
see all…
RESOURCE TYPE
Article
26 results
26
LANGUAGE
English
26 results
26
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