Showing 31 - 40 results of 42 for search '"Latency."', query time: 0.02s Refine Results
  1. 31

    Fast factorization architecture in soft-decision Reed-Solomon decoding. by Xinmiao Zhang

    Article

    Fast factorization architecture in soft-decision Reed-Solomon decoding.
  2. 32

    Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders. by Dobkin, R.

    Article

    Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders.
  3. 33

    VLSI architectural design tradeoffs for sliding-window log-MAP decoders. by Chien-Ming Wu

    Article

    VLSI architectural design tradeoffs for sliding-window log-MAP decoders.
  4. 34

    Memory sub-banking scheme for high throughput MAP-based SISO decoders. by Tiwari, M.

    Article

    Memory sub-banking scheme for high throughput MAP-based SISO decoders.
  5. 35

    A forward body-biased low-leakage SRAM cache device, circuit and architecture considerations. by Kim, C.H

    Article

    A forward body-biased low-leakage SRAM cache device, circuit and architecture considerations.
  6. 36

    Scalable routing strategies for ad hoc wireless networks. by Iwata, A.

    Article

    Scalable routing strategies for ad hoc wireless networks.
  7. 37

    The effects of on-demand behavior in routing protocols for multihop wireless ad hoc networks. by Maltz, D.A

    Article

    The effects of on-demand behavior in routing protocols for multihop wireless ad hoc networks.
  8. 38

    What ails broadband?. by Cooper, M.

    Published in IEEE spectrum
    Article

    What ails broadband?.
  9. 39

    Coding for system-on-chip networks a unified framework. by Sridhara, S.R

    Article

    Coding for system-on-chip networks a unified framework.
  10. 40

    Combined circuit and architectural level variable supply-voltage scaling for low power. by Hai Li

    Article

    Combined circuit and architectural level variable supply-voltage scaling for low power.

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