Отображение 121 - 130 результаты of 174 для поиска '"Interconnecting."', время запроса: 0.02сек. Отмена результатов
  1. 121

    Fault Tolerance of Switch Blocks and Switch Block Arrays in FPGA. по Huang, J.

    Опубликовано в: IEEE Transactions on VLSI systems
    Статья

    Fault Tolerance of Switch Blocks and Switch Block Arrays in FPGA.
  2. 122

    ATOMi An Algorithm for Circuit Partitioning Into Multiple FPGAs Using Time-Multiplexed, Off-Chip, Multicasting Interconnection Architecture. по Kwon, Y.-S

    Опубликовано в: IEEE Transactions on VLSI systems
    Статья

    ATOMi An Algorithm for Circuit Partitioning Into Multiple FPGAs Using Time-Multiplexed, Off-Chip, Multicasting Interconnection Architecture.
  3. 123

    2.5-dimensional VLSI system integration. по Yangdong Deng

    Опубликовано в: IEEE Transactions on VLSI systems
    Статья

    2.5-dimensional VLSI system integration.
  4. 124

    Analysis of load frequency control performance assessment criteria. по Gross, G.

    Опубликовано в: IEEE Transactions on power systems
    Статья

    Analysis of load frequency control performance assessment criteria.
  5. 125

    POMR a power-aware interconnect optimization methodology. по Youssef, A.

    Опубликовано в: IEEE Transactions on VLSI systems
    Статья

    POMR a power-aware interconnect optimization methodology.
  6. 126

    Optimization of throughput performance for low-power VLSI interconnects. по Deodhar, V.V

    Опубликовано в: IEEE Transactions on VLSI systems
    Статья

    Optimization of throughput performance for low-power VLSI interconnects.
  7. 127

    On the impact of on-chip inductance on signal nets under the influence of power grid noise. по Chen, T.

    Опубликовано в: IEEE Transactions on VLSI systems
    Статья

    On the impact of on-chip inductance on signal nets under the influence of power grid noise.
  8. 128

    Design of a 3-D fully depleted SOI computational RAM. по Koob, J.C

    Опубликовано в: IEEE Transactions on VLSI systems
    Статья

    Design of a 3-D fully depleted SOI computational RAM.
  9. 129

    Analytical test buffer design for differential signaling I по Sanghyeon Baeg

    Опубликовано в: IEEE Transactions on VLSI systems
    Статья

    Analytical test buffer design for differential signaling I
  10. 130

    Shielding effect of on-chip interconnect inductance. по El-Moursy, M.A

    Опубликовано в: IEEE Transactions on VLSI systems
    Статья

    Shielding effect of on-chip interconnect inductance.

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