Showing 801 - 810 results of 831 for search '"Integrated circuits."', query time: 0.02s Refine Results
  1. 801

    POMR a power-aware interconnect optimization methodology. by Youssef, A.

    Article

    POMR a power-aware interconnect optimization methodology.
  2. 802

    Design of a 3-D fully depleted SOI computational RAM. by Koob, J.C

    Article

    Design of a 3-D fully depleted SOI computational RAM.
  3. 803

    Shielding effect of on-chip interconnect inductance. by El-Moursy, M.A

    Article

    Shielding effect of on-chip interconnect inductance.
  4. 804

    Efficient shield insertion for inductive noise reduction in nanometer technologies. by Elgamel, M.A

    Article

    Efficient shield insertion for inductive noise reduction in nanometer technologies.
  5. 805

    Design of wireless on-wafer submicron characterization system. by Moore, B.

    Article

    Design of wireless on-wafer submicron characterization system.
  6. 806

    Interpretation of rent's rule for ultralarge-scale integrated circuit designs, with an application to wirelength distribution models. by Lanzerotti, M.Y

    Article

    Interpretation of rent's rule for ultralarge-scale integrated circuit designs, with an application to wirelength distribution models.
  7. 807

    Improving the stuck-at fault coverage of functional test sequences by using limited-scan operations. by Pomeranz, I.

    Article

    Improving the stuck-at fault coverage of functional test sequences by using limited-scan operations.
  8. 808

    Overview of a compiler for synthesizing MATLAB programs onto FPGAs. by Banerjee, P.

    Article

    Overview of a compiler for synthesizing MATLAB programs onto FPGAs.
  9. 809

    Substrate coupling in digital circuits in mixed-signal smart-power systems. by Secareanu, R.M

    Article

    Substrate coupling in digital circuits in mixed-signal smart-power systems.
  10. 810

    A jitter characterization system using a component-invariant Vernier delay line. by Chan, A.H

    Article

    A jitter characterization system using a component-invariant Vernier delay line.

Search Tools: