Showing 21 - 23 results of 23 for search '"Integrated circuit testing."', query time: 0.02s Refine Results
  1. 21

    POMR a power-aware interconnect optimization methodology. by Youssef, A.

    Article

    POMR a power-aware interconnect optimization methodology.
  2. 22

    Design of a 3-D fully depleted SOI computational RAM. by Koob, J.C

    Article

    Design of a 3-D fully depleted SOI computational RAM.
  3. 23

    Design of wireless on-wafer submicron characterization system. by Moore, B.

    Article

    Design of wireless on-wafer submicron characterization system.

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