Canlyniadau Chwilio - "High-level synthesis."

  • Dangos 1 - 6 canlyniadau o 6
Mireinio'r Canlyniadau
  1. 1

    Unification of scheduling, binding, and retiming to reduce power consumption under timings and resources constraints. gan Chabini, N.

    Erthygl


    Delwedd Flaen
  2. 2

    Efficient metrics and high-level synthesis for dynamically reconfigurable logic. gan Meribout, M.

    Erthygl


    Delwedd Flaen
  3. 3

    Algorithm level recomputing using allocation diversity a register transfer level approach to time redundancy-based concurrent error detection. gan Kaijie Wu

    Erthygl


    Delwedd Flaen
  4. 4

    Automatic test pattern generation for functional register-transfer level circuits using assignment decision diagrams. gan Ghosh, I.

    Erthygl


    Delwedd Flaen
  5. 5

    Memory binding for performance optimization of control-flow intensive behavioral descriptions. gan Khouri, K.S

    Erthygl


    Delwedd Flaen
  6. 6

    Overview of a compiler for synthesizing MATLAB programs onto FPGAs. gan Banerjee, P.

    Erthygl


    Delwedd Flaen

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