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Unification of scheduling, binding, and retiming to reduce power consumption under timings and resources constraints.
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Chabini, N.
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IEEE Transactions on VLSI systems
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Efficient metrics and high-level synthesis for dynamically reconfigurable logic.
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Meribout, M.
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Algorithm level recomputing using allocation diversity a register transfer level approach to time redundancy-based concurrent error detection.
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Kaijie Wu
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IEEE Transactions on computer-aided design of integrated circuits and systems
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Automatic test pattern generation for functional register-transfer level circuits using assignment decision diagrams.
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Ghosh, I.
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Memory binding for performance optimization of control-flow intensive behavioral descriptions.
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Khouri, K.S
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Overview of a compiler for synthesizing MATLAB programs onto FPGAs.
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Banerjee, P.
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CAMPUS
Diliman
6 results
6
DATABASE
Union Catalog (Buklod)
6 results
6
UNIT LIBRARY
College of Engineering Library II
6 results
6
RESOURCE TYPE
Article
6 results
6
AUTHOR
Banerjee, P.
1 results
1
Chabini, N.
1 results
1
Ghosh, I.
1 results
1
Kaijie Wu
1 results
1
Khouri, K.S
1 results
1
Meribout, M.
1 results
1
LANGUAGE
English
6 results
6
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