Mostrando 231 - 240 Resultados de 249 Para Buscar '"Hardware"', tiempo de consulta: 0.02s Limitar resultados
  1. 231

    Digital filter synthesis based on an algorithm to generate all minimal signed digit representations. por In-Cheol Park

    Artículo

    Digital filter synthesis based on an algorithm to generate all minimal signed digit representations.
  2. 232

    Algorithm level recomputing using allocation diversity a register transfer level approach to time redundancy-based concurrent error detection. por Kaijie Wu

    Artículo

    Algorithm level recomputing using allocation diversity a register transfer level approach to time redundancy-based concurrent error detection.
  3. 233

    Testing of core-based systems-on-a-chip. por Ravi, S.

    Artículo

    Testing of core-based systems-on-a-chip.
  4. 234

    A digital vision chip specialized for high-speed target tracking. por Komuro, T.

    Artículo

    A digital vision chip specialized for high-speed target tracking.
  5. 235

    FAIR a hardware architecture for real-time 3-D image registration. por Castro-Pareja, C.R

    Artículo

    FAIR a hardware architecture for real-time 3-D image registration.
  6. 236

    A real-time hardware fault detector using an artificial neural network for distance protection. por Venkatesan, R.

    Artículo

    A real-time hardware fault detector using an artificial neural network for distance protection.
  7. 237

    Extended-range PMSM sensorless speed drive based on stochastic filtering. por Bolognani, S.

    Artículo

    Extended-range PMSM sensorless speed drive based on stochastic filtering.
  8. 238

    Input space adaptive design a high-level methodology for optimizing energy and performance. por Weidong Wang

    Artículo

    Input space adaptive design a high-level methodology for optimizing energy and performance.
  9. 239

    Efficient metrics and high-level synthesis for dynamically reconfigurable logic. por Meribout, M.

    Artículo

    Efficient metrics and high-level synthesis for dynamically reconfigurable logic.
  10. 240

    Pel reconstruction on FPGA-augmented TriMedia. por Sima, M.

    Artículo

    Pel reconstruction on FPGA-augmented TriMedia.

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