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Flip-flop design in nanometer CMOS from high speed to low energy
Published 2015Available for University of the Philippines System via SpringerLink. Click here to access
Also available remotely for University of the Philippines System via SpringerLink. Click here to access thru EZproxy
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Scaling trends of on-chip power distribution noise.
Published in IEEE Transactions on VLSI systemsArticle -
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PSPC leaps into production of next-gen memory chips.
Published in Manila BulletinGet full text
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