Showing 61 - 70 results of 98 for search '"Field programmable gate arrays."', זמן שאילתה: 0.02s Refine Results
  1. 61

    A novel FPGA architecture supporting wide, shallow memories. מאת Oldridge, S.W

    הוצא לאור ב IEEE Transactions on VLSI systems
    Article

    A novel FPGA architecture supporting wide, shallow memories.
  2. 62

    Virtex FPGA implementation of a pipelined adaptive LMS predictor for electronic support measures receivers. מאת Lok-Kee Ting

    הוצא לאור ב IEEE Transactions on VLSI systems
    Article

    Virtex FPGA implementation of a pipelined adaptive LMS predictor for electronic support measures receivers.
  3. 63

    Layout techniques for FPGA switch blocks. מאת Schmit, H.

    הוצא לאור ב IEEE Transactions on VLSI systems
    Article

    Layout techniques for FPGA switch blocks.
  4. 64

    Online BIST and BIST-based diagnosis of FPGA logic blocks. מאת Abramovici, M.

    הוצא לאור ב IEEE Transactions on VLSI systems
    Article

    Online BIST and BIST-based diagnosis of FPGA logic blocks.
  5. 65

    Interconnect accelerating techniques for sub-100-nm gigascale systems. מאת Hong-Yi Huang

    הוצא לאור ב IEEE Transactions on VLSI systems
    Article

    Interconnect accelerating techniques for sub-100-nm gigascale systems.
  6. 66

    Power estimation techniques for FPGAs. מאת Anderson, J.H

    הוצא לאור ב IEEE Transactions on VLSI systems
    Article

    Power estimation techniques for FPGAs.
  7. 67

    Sequential delay budgeting with interconnect prediction. מאת Chao-Yang Yeh

    הוצא לאור ב IEEE Transactions on VLSI systems
    Article

    Sequential delay budgeting with interconnect prediction.
  8. 68

    Design of FPGA interconnect for multilevel metallization. מאת DeHon, A.

    הוצא לאור ב IEEE Transactions on VLSI systems
    Article

    Design of FPGA interconnect for multilevel metallization.
  9. 69

    Unifying mesh- and tree-based programmable interconnect. מאת DeHon, A.

    הוצא לאור ב IEEE Transactions on VLSI systems
    Article

    Unifying mesh- and tree-based programmable interconnect.
  10. 70

    Highly efficient, limited range multipliers for LUT-based FPGA architectures. מאת Turner, R.H

    הוצא לאור ב IEEE Transactions on VLSI systems
    Article

    Highly efficient, limited range multipliers for LUT-based FPGA architectures.

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