Results for "Field programmable gate array."

Results for "Field programmable gate array." Showing 1 - 50 results of 98 Laminas_Feed_Writer 2 (https://getlaminas.org) https://tuklas.up.edu.ph/Search/Results?sort=last_indexed+desc&limit=50&lookfor=%22Field+programmable+gate+array.%22&type=Subject&lng=en 98 0 50 Technology mapping for LUT-based FPGA Fri, 01 Jan 2021 15:45:40 +0800 https://tuklas.up.edu.ph/Record/UP-8027295163992825335 https://tuklas.up.edu.ph/Record/UP-8027295163992825335 Kubica, Marcin Electronic Resource 2021 Kubica, Marcin 0 Implementation of a Least Mean Squares (LMS) based ITU-T G.168 digital network echo canceller on a Xilinx Virtex 5 SXT FPGA https://tuklas.up.edu.ph/Record/UP-99796217609084990 https://tuklas.up.edu.ph/Record/UP-99796217609084990 Medina, Keone Karl Apadua Thesis Medina, Keone Karl Apadua 0 Implementation of occupancy grid-based mapping algorithm on ATRV-mini platform with Openwrt https://tuklas.up.edu.ph/Record/UP-99796217608650494 https://tuklas.up.edu.ph/Record/UP-99796217608650494 dela Cruz, Divina Joy M. Thesis dela Cruz, Divina Joy M. 0 Functionality-enhanced devices an alternative to Moore's Law Mon, 01 Jan 2018 15:45:40 +0800 https://tuklas.up.edu.ph/Record/UP-99796217613785845 https://tuklas.up.edu.ph/Record/UP-99796217613785845 Electronic Resource 2018 0 Fuzzy logic type 1 and type 2 based on LabVIEW FPGA Fri, 01 Jan 2016 15:45:40 +0800 https://tuklas.up.edu.ph/Record/UP-99796217613012805 https://tuklas.up.edu.ph/Record/UP-99796217613012805 Ponce-Cruz, Pedro Electronic Resource 2016 Ponce-Cruz, Pedro 0 Authentication technologies for cloud computing, IoT and big data Tue, 01 Jan 2019 15:45:40 +0800 https://tuklas.up.edu.ph/Record/UP-99796217613765212 https://tuklas.up.edu.ph/Record/UP-99796217613765212 Electronic Resource 2019 0 Implementation of a dynamically reconfigurable encoder-decoder multiplier system using FPGAs Fri, 01 Jan 1999 15:45:40 +0800 https://tuklas.up.edu.ph/Record/UP-99796217608094551 https://tuklas.up.edu.ph/Record/UP-99796217608094551 Antonio, Ginia G. Thesis 1999 Antonio, Ginia G. 0 Practical FPGA programming in C Sat, 01 Jan 2005 15:45:40 +0800 https://tuklas.up.edu.ph/Record/UP-99796217608533018 https://tuklas.up.edu.ph/Record/UP-99796217608533018 Pellerin, David Book 2005 Pellerin, David 0 Implementation of an ARM7 dual-core microprocessor using Xilinx Spartan-IIE Family of FPGA Mon, 01 Jan 2007 15:45:40 +0800 https://tuklas.up.edu.ph/Record/UP-99796217608094556 https://tuklas.up.edu.ph/Record/UP-99796217608094556 Busok, Gino Jr. C. Thesis 2007 Busok, Gino Jr. C. 0 Field-programmable gate arrays reconfigurable logic for rapid prototyping and implementation of digital systems Sun, 01 Jan 1995 15:45:40 +0800 https://tuklas.up.edu.ph/Record/UP-99796217603084602 https://tuklas.up.edu.ph/Record/UP-99796217603084602 Oldfield, John V. 1933- Book 1995 Oldfield, John V. 1933- 0 Design recipes for FPGAs Mon, 01 Jan 2007 15:45:40 +0800 https://tuklas.up.edu.ph/Record/UP-99796217608914067 https://tuklas.up.edu.ph/Record/UP-99796217608914067 Wilson, Peter R. (Peter Robert) 1939- Book 2007 Wilson, Peter R. (Peter Robert) 1939- 0 FPGA prototyping by VHDL examples Xilinx Spartan -3 version Tue, 01 Jan 2008 15:45:40 +0800 https://tuklas.up.edu.ph/Record/UP-99796217608914071 https://tuklas.up.edu.ph/Record/UP-99796217608914071 Chu, Pong P. 1959- Book 2008 Chu, Pong P. 1959- 0 Rapid prototyping of digital systems Sat, 01 Jan 2000 15:45:40 +0800 https://tuklas.up.edu.ph/Record/UP-99796217603017449 https://tuklas.up.edu.ph/Record/UP-99796217603017449 Hamblen, James O. Book 2000 Hamblen, James O. 0 IEEE Workshop on FPGAs for Custom Computing Machines proceedings, April 5-7, 1993, Napa, California Fri, 01 Jan 1993 15:45:40 +0800 https://tuklas.up.edu.ph/Record/UP-99796217603051529 https://tuklas.up.edu.ph/Record/UP-99796217603051529 Book 1993 0 Characterization of a hardware implementation of a Parallel Sequence Spread Spectrum (PSSS) modulation scheme https://tuklas.up.edu.ph/Record/UP-99796217608947308 https://tuklas.up.edu.ph/Record/UP-99796217608947308 Lorenzo, Romarie Urgel Thesis Lorenzo, Romarie Urgel 0 FPGA implementation of space-time trellis decoder https://tuklas.up.edu.ph/Record/UP-99796217608369748 https://tuklas.up.edu.ph/Record/UP-99796217608369748 Calayag, Marciano Jr. S. Thesis Calayag, Marciano Jr. S. 0 Embedded core design with FPGAs Mon, 01 Jan 2007 15:45:40 +0800 https://tuklas.up.edu.ph/Record/UP-99796217603100940 https://tuklas.up.edu.ph/Record/UP-99796217603100940 Navabi, Zainalabedin Book 2007 Navabi, Zainalabedin 0 Digital signal processing with field programmable gate arrays Wed, 01 Jan 2014 15:45:40 +0800 https://tuklas.up.edu.ph/Record/UP-99796217612770675 https://tuklas.up.edu.ph/Record/UP-99796217612770675 Meyer-Baese, U. (Uwe) 1964- Electronic Resource 2014 Meyer-Baese, U. (Uwe) 1964- 0 A USB 2.0 controller for an ARM7TDM-S processor implemented in FPGA Sat, 01 Jan 2011 15:45:40 +0800 https://tuklas.up.edu.ph/Record/UP-99796217611173214 https://tuklas.up.edu.ph/Record/UP-99796217611173214 Difuntorum, John Keithley L. Thesis 2011 Difuntorum, John Keithley L. 0 FPGA prototyping by Verilog examples Xilinx Spartan -3 version Tue, 01 Jan 2008 15:45:40 +0800 https://tuklas.up.edu.ph/Record/UP-99796217612240626 https://tuklas.up.edu.ph/Record/UP-99796217612240626 Chu, Pong P. 1959- Electronic Resource 2008 Chu, Pong P. 1959- 0 Implementation of low cost fpga remote laboratory https://tuklas.up.edu.ph/Record/UP-99796217612351377 https://tuklas.up.edu.ph/Record/UP-99796217612351377 Hoang Thang Manh Article Hoang Thang Manh 0 Functional verification of dynamically reconfigurable FPGA-based systems Thu, 01 Jan 2015 15:45:40 +0800 https://tuklas.up.edu.ph/Record/UP-99796217612769892 https://tuklas.up.edu.ph/Record/UP-99796217612769892 Gong, Lingkan Electronic Resource 2015 Gong, Lingkan 0 Hands-on experience with Altera FPGA development boards Mon, 01 Jan 2018 15:45:40 +0800 https://tuklas.up.edu.ph/Record/UP-99796217613331502 https://tuklas.up.edu.ph/Record/UP-99796217613331502 Parab, Jivan S. Electronic Resource 2018 Parab, Jivan S. 0 FPGA based accelerators for financial applications Thu, 01 Jan 2015 15:45:40 +0800 https://tuklas.up.edu.ph/Record/UP-99796217612749732 https://tuklas.up.edu.ph/Record/UP-99796217612749732 Electronic Resource 2015 0 FPGA design best practices for team-based reuse Thu, 01 Jan 2015 15:45:40 +0800 https://tuklas.up.edu.ph/Record/UP-99796217612749733 https://tuklas.up.edu.ph/Record/UP-99796217612749733 Simpson, Philip A. Electronic Resource 2015 Simpson, Philip A. 0 Architecture exploration of FPGA based accelerators for bioinformatics applications Fri, 01 Jan 2016 15:45:40 +0800 https://tuklas.up.edu.ph/Record/UP-99796217612935816 https://tuklas.up.edu.ph/Record/UP-99796217612935816 Varma, B. Sharat Chandra Electronic Resource 2016 Varma, B. Sharat Chandra 0 The Chimaera reconfigurable functional unit. https://tuklas.up.edu.ph/Record/UP-99796217609624600 https://tuklas.up.edu.ph/Record/UP-99796217609624600 Hauck, S. Article Hauck, S. 0 Multiple-symbol parallel decoding for variable length codes. https://tuklas.up.edu.ph/Record/UP-99796217609624397 https://tuklas.up.edu.ph/Record/UP-99796217609624397 Nikara, J. Article Nikara, J. 0 A jitter characterization system using a component-invariant Vernier delay line. https://tuklas.up.edu.ph/Record/UP-99796217609624617 https://tuklas.up.edu.ph/Record/UP-99796217609624617 Chan, A.H Article Chan, A.H 0 Hardware implementation of finite-field arithmetic Thu, 01 Jan 2009 15:45:40 +0800 https://tuklas.up.edu.ph/Record/UP-99796217609243818 https://tuklas.up.edu.ph/Record/UP-99796217609243818 Deschamps, Jean-Pierre 1945- Book 2009 Deschamps, Jean-Pierre 1945- 0 Interconnect accelerating techniques for sub-100-nm gigascale systems. https://tuklas.up.edu.ph/Record/UP-99796217609611789 https://tuklas.up.edu.ph/Record/UP-99796217609611789 Hong-Yi Huang Article Hong-Yi Huang 0 Design and implementation of an FPGA-based GPR and TDR system for soil investigations https://tuklas.up.edu.ph/Record/UP-99796217609277636 https://tuklas.up.edu.ph/Record/UP-99796217609277636 Thesis 0 A family of self-normalizing carrier lock detectors and ES https://tuklas.up.edu.ph/Record/UP-99796217609625103 https://tuklas.up.edu.ph/Record/UP-99796217609625103 Linn, Y. Article Linn, Y. 0 The effect of LUT and cluster size on deep-submicron FPGA performance and density. https://tuklas.up.edu.ph/Record/UP-99796217609624571 https://tuklas.up.edu.ph/Record/UP-99796217609624571 Ahmed, E. Article Ahmed, E. 0 A software https://tuklas.up.edu.ph/Record/UP-99796217609624552 https://tuklas.up.edu.ph/Record/UP-99796217609624552 Skliarova, I. Article Skliarova, I. 0 Design of packet-fair queuing schedulers using a RAM-based searching engine. https://tuklas.up.edu.ph/Record/UP-99796217609350669 https://tuklas.up.edu.ph/Record/UP-99796217609350669 Chao, H.J Article Chao, H.J 0 Overview of a compiler for synthesizing MATLAB programs onto FPGAs. https://tuklas.up.edu.ph/Record/UP-99796217609624580 https://tuklas.up.edu.ph/Record/UP-99796217609624580 Banerjee, P. Article Banerjee, P. 0 VHDL 101 everything you need to know to get started Sat, 01 Jan 2011 15:45:40 +0800 https://tuklas.up.edu.ph/Record/UP-99796217610121363 https://tuklas.up.edu.ph/Record/UP-99796217610121363 Kafig, William Book 2011 Kafig, William 0 Design-for-testability for embedded delay-locked loops. https://tuklas.up.edu.ph/Record/UP-99796217609599352 https://tuklas.up.edu.ph/Record/UP-99796217609599352 Egan, T. Article Egan, T. 0 InvMixColumn decomposition and multilevel resource sharing in AES implementations. https://tuklas.up.edu.ph/Record/UP-99796217609599354 https://tuklas.up.edu.ph/Record/UP-99796217609599354 Fischer, V. Article Fischer, V. 0 Virtex FPGA implementation of a pipelined adaptive LMS predictor for electronic support measures receivers. https://tuklas.up.edu.ph/Record/UP-99796217609611615 https://tuklas.up.edu.ph/Record/UP-99796217609611615 Lok-Kee Ting Article Lok-Kee Ting 0 Layout techniques for FPGA switch blocks. https://tuklas.up.edu.ph/Record/UP-99796217609611618 https://tuklas.up.edu.ph/Record/UP-99796217609611618 Schmit, H. Article Schmit, H. 0 FPGA prototyping by VHDL examples Xilinx Spartan-3 version Tue, 01 Jan 2008 15:45:40 +0800 https://tuklas.up.edu.ph/Record/UP-99796217612240436 https://tuklas.up.edu.ph/Record/UP-99796217612240436 Chu, Pong P. 1959- Electronic Resource 2008 Chu, Pong P. 1959- 0 Prototyping of concurrent control systems implemented in FPGA devices Sun, 01 Jan 2017 15:45:40 +0800 https://tuklas.up.edu.ph/Record/UP-99796217613118121 https://tuklas.up.edu.ph/Record/UP-99796217613118121 Wisniewski, Remigiusz G. Electronic Resource 2017 Wisniewski, Remigiusz G. 0 ATRV-mini platform development for navigation and mapping Mon, 01 Jan 2007 15:45:40 +0800 https://tuklas.up.edu.ph/Record/UP-99796217613562281 https://tuklas.up.edu.ph/Record/UP-99796217613562281 Talens, Angelito N. Thesis 2007 Talens, Angelito N. 0 High performance integer arithmetic circuit design on FPGA architecture, implementation and design automation Fri, 01 Jan 2016 15:45:40 +0800 https://tuklas.up.edu.ph/Record/UP-99796217613033490 https://tuklas.up.edu.ph/Record/UP-99796217613033490 Palchaudhuri, Ayan Electronic Resource 2016 Palchaudhuri, Ayan 0 Digital system design with FPGA implementation using Verilog and VHDL Sun, 01 Jan 2017 15:45:40 +0800 https://tuklas.up.edu.ph/Record/UP-99796217613218399 https://tuklas.up.edu.ph/Record/UP-99796217613218399 Ünsalan, Cem Electronic Resource 2017 Ünsalan, Cem 0 Design of FPGA-based computing systems with OpenCL Mon, 01 Jan 2018 15:45:40 +0800 https://tuklas.up.edu.ph/Record/UP-99796217613314347 https://tuklas.up.edu.ph/Record/UP-99796217613314347 Waidyasooriya, Hasitha Muthumala Electronic Resource 2018 Waidyasooriya, Hasitha Muthumala 0 Reconfigurable field programmable gate arrays for mission-critical applications Sat, 01 Jan 2011 15:45:40 +0800 https://tuklas.up.edu.ph/Record/UP-99796217611212077 https://tuklas.up.edu.ph/Record/UP-99796217611212077 Battezzati, Niccolò Electronic Resource 2011 Battezzati, Niccolò 0 VLSI design a practical guide for FPGA and ASIC implementations Sat, 01 Jan 2011 15:45:40 +0800 https://tuklas.up.edu.ph/Record/UP-99796217611190522 https://tuklas.up.edu.ph/Record/UP-99796217611190522 Chandrasetty, Vikram Arkalgud Electronic Resource 2011 Chandrasetty, Vikram Arkalgud 0