Search Results - "Errors"

661

40-43-Gb/s OC-768 16 1 MUX by Hai Tao

Published in IEEE Journal of solid state circuits

Article

662

A self-tuning DVS processor using delay-error detection and correction. by Das, S.

Published in IEEE Journal of solid state circuits

Article

A self-tuning DVS processor using delay-error detection and correction.

663

A direct digital frequency synthesizer with fourth-order phase domain ΔΣ noise shaper and 12-bit current-steering DAC. by Fa Foster Dai

Published in IEEE Journal of solid state circuits

Article

A direct digital frequency synthesizer with fourth-order phase domain ΔΣ noise shaper and 12-bit current-steering DAC.

664

A 1 Tb by Miura, N.

Published in IEEE Journal of solid state circuits

Article

665

An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I by Kim, K.-h

Published in IEEE Journal of solid state circuits

Article

An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I

666

Intrastream synchronization for continuous media streams a survey of playout schedulers. by Laoutaris, N.

Published in IEEE Network : the magazine of global information exchange

Article

Intrastream synchronization for continuous media streams a survey of playout schedulers.

667

Joint admission by Te-Kai Liu

Published in IEEE Journal on selected areas in communications

Article

668

Antenna-sector time-division multiple access for broadband indoor wireless systems. by Macedo, A.S

Published in IEEE Journal on selected areas in communications

Article

Antenna-sector time-division multiple access for broadband indoor wireless systems.

669

A blind adaptive decorrelating detector for CDMA systems. by Ulukus, S.

Published in IEEE Journal on selected areas in communications

Article

A blind adaptive decorrelating detector for CDMA systems.

670

A CDMA interference canceling receiver with an adaptive blind array. by Ghazi-Moghadam, V.

Published in IEEE Journal on selected areas in communications

Article

40-43-Gb/s OC-768 16 1 MUX by Hai Tao

A self-tuning DVS processor using delay-error detection and correction. by Das, S.

A direct digital frequency synthesizer with fourth-order phase domain ΔΣ noise shaper and 12-bit current-steering DAC. by Fa Foster Dai

A 1 Tb by Miura, N.

An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I by Kim, K.-h

Intrastream synchronization for continuous media streams a survey of playout schedulers. by Laoutaris, N.

Joint admission by Te-Kai Liu

Antenna-sector time-division multiple access for broadband indoor wireless systems. by Macedo, A.S

A blind adaptive decorrelating detector for CDMA systems. by Ulukus, S.

A CDMA interference canceling receiver with an adaptive blind array. by Ghazi-Moghadam, V.

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