Zoekresultaten - "Embedded core."

1

A unified approach to reduce SOC test data volume, scan power and testing time. door Chandra, A.

Gepubliceerd in IEEE Transactions on computer-aided design of integrated circuits and systems

Artikel

A unified approach to reduce SOC test data volume, scan power and testing time.

2

Wrapper design for multifrequency IP cores. door Qiang Xu

Gepubliceerd in IEEE Transactions on VLSI systems

Artikel

Wrapper design for multifrequency IP cores.

3

Nine-coded compression technique for testing embedded cores in SoCs. door Tehranipoor, M.

Gepubliceerd in IEEE Transactions on VLSI systems

Artikel

Nine-coded compression technique for testing embedded cores in SoCs.

4

Test data compression technique for embedded cores using virtual scan chains. door Jas, A.

Gepubliceerd in IEEE Transactions on VLSI systems

Artikel

Test data compression technique for embedded cores using virtual scan chains.

5

Modular and rapid testing of SOCs with unwrapped logic blocks. door Qiang Xu

Gepubliceerd in IEEE Transactions on VLSI systems

Artikel

Modular and rapid testing of SOCs with unwrapped logic blocks.

6

Testing ASICs with multiple identical cores. door Yuejian Wu

Gepubliceerd in IEEE Transactions on computer-aided design of integrated circuits and systems

Artikel

Testing ASICs with multiple identical cores.

7

Automatic interconnection rectification for SoC design verification based on the port order fault model. door Chun-Yao Wang

Gepubliceerd in IEEE Transactions on computer-aided design of integrated circuits and systems

Artikel

Automatic interconnection rectification for SoC design verification based on the port order fault model.

8

Formulating SoC test scheduling as a network transportation problem. door Koranne, S.

Gepubliceerd in IEEE Transactions on computer-aided design of integrated circuits and systems

Artikel

Formulating SoC test scheduling as a network transportation problem.

9

System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints. door Iyengar, V.

Gepubliceerd in IEEE Transactions on computer-aided design of integrated circuits and systems

Artikel

System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints.

10

System-on-a-chip test-data compression and decompression architectures based on Golomb codes. door Chandra, A.

Gepubliceerd in IEEE Transactions on computer-aided design of integrated circuits and systems

Artikel

A unified approach to reduce SOC test data volume, scan power and testing time. door Chandra, A.

Wrapper design for multifrequency IP cores. door Qiang Xu

Nine-coded compression technique for testing embedded cores in SoCs. door Tehranipoor, M.

Test data compression technique for embedded cores using virtual scan chains. door Jas, A.

Modular and rapid testing of SOCs with unwrapped logic blocks. door Qiang Xu

Testing ASICs with multiple identical cores. door Yuejian Wu

Automatic interconnection rectification for SoC design verification based on the port order fault model. door Chun-Yao Wang

Formulating SoC test scheduling as a network transportation problem. door Koranne, S.

System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints. door Iyengar, V.

System-on-a-chip test-data compression and decompression architectures based on Golomb codes. door Chandra, A.

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