Suchergebnisse - "Embedded core."

1

A unified approach to reduce SOC test data volume, scan power and testing time. von Chandra, A.

Veröffentlicht in IEEE Transactions on computer-aided design of integrated circuits and systems

Artikel

A unified approach to reduce SOC test data volume, scan power and testing time.

2

Wrapper design for multifrequency IP cores. von Qiang Xu

Veröffentlicht in IEEE Transactions on VLSI systems

Artikel

Wrapper design for multifrequency IP cores.

3

Nine-coded compression technique for testing embedded cores in SoCs. von Tehranipoor, M.

Veröffentlicht in IEEE Transactions on VLSI systems

Artikel

Nine-coded compression technique for testing embedded cores in SoCs.

4

Test data compression technique for embedded cores using virtual scan chains. von Jas, A.

Veröffentlicht in IEEE Transactions on VLSI systems

Artikel

Test data compression technique for embedded cores using virtual scan chains.

5

Modular and rapid testing of SOCs with unwrapped logic blocks. von Qiang Xu

Veröffentlicht in IEEE Transactions on VLSI systems

Artikel

Modular and rapid testing of SOCs with unwrapped logic blocks.

6

Testing ASICs with multiple identical cores. von Yuejian Wu

Veröffentlicht in IEEE Transactions on computer-aided design of integrated circuits and systems

Artikel

Testing ASICs with multiple identical cores.

7

Automatic interconnection rectification for SoC design verification based on the port order fault model. von Chun-Yao Wang

Veröffentlicht in IEEE Transactions on computer-aided design of integrated circuits and systems

Artikel

Automatic interconnection rectification for SoC design verification based on the port order fault model.

8

Formulating SoC test scheduling as a network transportation problem. von Koranne, S.

Veröffentlicht in IEEE Transactions on computer-aided design of integrated circuits and systems

Artikel

Formulating SoC test scheduling as a network transportation problem.

9

System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints. von Iyengar, V.

Veröffentlicht in IEEE Transactions on computer-aided design of integrated circuits and systems

Artikel

System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints.

10

System-on-a-chip test-data compression and decompression architectures based on Golomb codes. von Chandra, A.

Veröffentlicht in IEEE Transactions on computer-aided design of integrated circuits and systems

Artikel

A unified approach to reduce SOC test data volume, scan power and testing time. von Chandra, A.

Wrapper design for multifrequency IP cores. von Qiang Xu

Nine-coded compression technique for testing embedded cores in SoCs. von Tehranipoor, M.

Test data compression technique for embedded cores using virtual scan chains. von Jas, A.

Modular and rapid testing of SOCs with unwrapped logic blocks. von Qiang Xu

Testing ASICs with multiple identical cores. von Yuejian Wu

Automatic interconnection rectification for SoC design verification based on the port order fault model. von Chun-Yao Wang

Formulating SoC test scheduling as a network transportation problem. von Koranne, S.

System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints. von Iyengar, V.

System-on-a-chip test-data compression and decompression architectures based on Golomb codes. von Chandra, A.

Suchwerkzeuge:

Treffer weiter einschränken

DATABASE

AUTHOR

RESOURCE TYPE

LANGUAGE