Εμφανίζονται 1 - 8 Αποτελέσματα από 8 για την αναζήτηση '"Drain current."', χρόνος αναζήτησης: 0,02δλ Περιορισμός αποτελεσμάτων
  1. 1

    A CAD methodology for optimizing transistor current and sizing in analog CMOS design. ανά Binkley, D.M

    Άρθρο

    A CAD methodology for optimizing transistor current and sizing in analog CMOS design.
  2. 2

    Elimination of kink phenomena and drain current hysteresis in InP-based HEMTs with a direct ohmic structure. ανά Sawada, K.

    Τόπος έκδοσης IEEE Transactions on electron devices
    Άρθρο

    Elimination of kink phenomena and drain current hysteresis in InP-based HEMTs with a direct ohmic structure.
  3. 3

    Pulsed measurements and circuit modeling of weak and strong avalanche effects in GaAs MESFETs and HEMTs. ανά Meneghesso, G.

    Τόπος έκδοσης IEEE Transactions on electron devices
    Άρθρο

    Pulsed measurements and circuit modeling of weak and strong avalanche effects in GaAs MESFETs and HEMTs.
  4. 4

    A novel technique for fabricating high reliable trench DMOSFETs using self-align technique and hydrogen annealing. ανά Jongdae Kim

    Τόπος έκδοσης IEEE Transactions on electron devices
    Άρθρο

    A novel technique for fabricating high reliable trench DMOSFETs using self-align technique and hydrogen annealing.
  5. 5

    Accounting for quantum effects and polysilicon depletion from weak to strong inversion in a charge-based design-oriented MOSFET model. ανά Lallement, C.

    Τόπος έκδοσης IEEE Transactions on electron devices
    Άρθρο

    Accounting for quantum effects and polysilicon depletion from weak to strong inversion in a charge-based design-oriented MOSFET model.
  6. 6

    A compact analytical model for asymmetric single-electron tunneling transistors. ανά Inokawa, H.

    Τόπος έκδοσης IEEE Transactions on electron devices
    Άρθρο

    A compact analytical model for asymmetric single-electron tunneling transistors.
  7. 7

    Modeling subthreshold SOI logic for static timing analysis. ανά Valentian, A.

    Τόπος έκδοσης IEEE Transactions on VLSI systems
    Άρθρο

    Modeling subthreshold SOI logic for static timing analysis.
  8. 8

    A compact analytical model for asymmetric single-electron tunneling transistors. ανά Inokawa, H.

    Τόπος έκδοσης IEEE Transactions on electron devices
    Άρθρο

    A compact analytical model for asymmetric single-electron tunneling transistors.

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