Zobrazuji výsledky 12 481 - 12 490 z 13 981 pro vyhledávání '"Design."', doba hledání: 0,06 s. Upřesnit hledání
  1. 12481

    Design and implementation of pipelined analog-to-digital converters in a 90nm CMOS process Autor Dizon, Aaron Galvez

    Diplomová práce

    Design and implementation of pipelined analog-to-digital converters in a 90nm CMOS process
  2. 12482

    Development of a control system with PC interface for a selective compliant articulated robot arm Autor Buyao, Reynald C.

    Diplomová práce

    Development of a control system with PC interface for a selective compliant articulated robot arm
  3. 12483

    Simulation of transmission line matching networks in GaAs MMIC applications Autor Monsod, Trevor Andrei Free A.

    Diplomová práce

    Simulation of transmission line matching networks in GaAs MMIC applications
  4. 12484

    Design and implementation of directional couplers using waveguides and microstrip transmission lines Autor Del Rosario, Cennen C.

    Diplomová práce

    Design and implementation of directional couplers using waveguides and microstrip transmission lines
  5. 12485

    Development of a linear motor based gantry Autor Brocoy, Jonel A.

    Diplomová práce

    Development of a linear motor based gantry
  6. 12486

    A CMOS switched transconductor mixer. Autor Klumperink, E.A.M

    Článek

    A CMOS switched transconductor mixer.
  7. 12487

    Design and application of CMOS bulk input scheme. Autor Hong-Yi Huang

    Článek

    Design and application of CMOS bulk input scheme.
  8. 12488

    A low-power DS-CDMA RAKE receiver utilizing resource allocation techniques. Autor Eltawil, A.M

    Článek

    A low-power DS-CDMA RAKE receiver utilizing resource allocation techniques.
  9. 12489

    Mobile multi-user ATM platforms architectures, design issues, and challenges. Autor Kumar, P.

    Článek

    Mobile multi-user ATM platforms architectures, design issues, and challenges.
  10. 12490

    A 20-GHz phase-locked loop for 40-gb Autor Jaeha Kim

    Článek

    A 20-GHz phase-locked loop for 40-gb

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