Отображение 1 - 10 результаты of 10 для поиска '"Design for testability."', время запроса: 0.02сек. Отмена результатов
  1. 1

    Testing big chips becomes an internal affair. по Runyon, S.

    Опубликовано в: IEEE spectrum
    Статья

    Testing big chips becomes an internal affair.
  2. 2

    Test pattern generation and clock disabling for simultaneous test time and power reduction. по Jih-Jeen Chen

    Статья

    Test pattern generation and clock disabling for simultaneous test time and power reduction.
  3. 3

    Design-for-testability and fault-tolerant techniques for FFT processors. по Shyue-Kung Lu

    Опубликовано в: IEEE Transactions on VLSI systems
    Статья

    Design-for-testability and fault-tolerant techniques for FFT processors.
  4. 4

    Test data compression technique for embedded cores using virtual scan chains. по Jas, A.

    Опубликовано в: IEEE Transactions on VLSI systems
    Статья

    Test data compression technique for embedded cores using virtual scan chains.
  5. 5

    Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations. по Qikai Chen

    Опубликовано в: IEEE Transactions on VLSI systems
    Статья

    Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations.
  6. 6

    Layout driven synthesis of multiple scan chains. по Rahimi, K.

    Статья

    Layout driven synthesis of multiple scan chains.
  7. 7

    Testing ASICs with multiple identical cores. по Yuejian Wu

    Статья

    Testing ASICs with multiple identical cores.
  8. 8

    Handling the pin overhead problem of DFTs for high-quality and at-speed tests. по Dong Xiang

    Статья

    Handling the pin overhead problem of DFTs for high-quality and at-speed tests.
  9. 9

    Autoscan a scan design without external scan inputs or outputs. по Pomeranz, I.

    Опубликовано в: IEEE Transactions on VLSI systems
    Статья

    Autoscan a scan design without external scan inputs or outputs.
  10. 10

    Design-for-testability for embedded delay-locked loops. по Egan, T.

    Опубликовано в: IEEE Transactions on VLSI systems
    Статья

    Design-for-testability for embedded delay-locked loops.

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