Showing 1 - 10 results of 10 for search '"Design for testability."', זמן שאילתה: 0.02s Refine Results
  1. 1

    Testing big chips becomes an internal affair. מאת Runyon, S.

    הוצא לאור ב IEEE spectrum
    Article

    Testing big chips becomes an internal affair.
  2. 2

    Test pattern generation and clock disabling for simultaneous test time and power reduction. מאת Jih-Jeen Chen

    Article

    Test pattern generation and clock disabling for simultaneous test time and power reduction.
  3. 3

    Design-for-testability and fault-tolerant techniques for FFT processors. מאת Shyue-Kung Lu

    הוצא לאור ב IEEE Transactions on VLSI systems
    Article

    Design-for-testability and fault-tolerant techniques for FFT processors.
  4. 4

    Test data compression technique for embedded cores using virtual scan chains. מאת Jas, A.

    הוצא לאור ב IEEE Transactions on VLSI systems
    Article

    Test data compression technique for embedded cores using virtual scan chains.
  5. 5

    Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations. מאת Qikai Chen

    הוצא לאור ב IEEE Transactions on VLSI systems
    Article

    Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations.
  6. 6

    Layout driven synthesis of multiple scan chains. מאת Rahimi, K.

    Article

    Layout driven synthesis of multiple scan chains.
  7. 7

    Testing ASICs with multiple identical cores. מאת Yuejian Wu

    Article

    Testing ASICs with multiple identical cores.
  8. 8

    Handling the pin overhead problem of DFTs for high-quality and at-speed tests. מאת Dong Xiang

    Article

    Handling the pin overhead problem of DFTs for high-quality and at-speed tests.
  9. 9

    Autoscan a scan design without external scan inputs or outputs. מאת Pomeranz, I.

    הוצא לאור ב IEEE Transactions on VLSI systems
    Article

    Autoscan a scan design without external scan inputs or outputs.
  10. 10

    Design-for-testability for embedded delay-locked loops. מאת Egan, T.

    הוצא לאור ב IEEE Transactions on VLSI systems
    Article

    Design-for-testability for embedded delay-locked loops.

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