Prikaz rezultata 1 – 10 od 10 za pretragu '"Design for testability."', vrijeme upita: 0,02s Detaljiziraj rezultate
  1. 1

    Testing big chips becomes an internal affair. od Runyon, S.

    Izdano u IEEE spectrum
    Članak

    Testing big chips becomes an internal affair.
  2. 2

    Test pattern generation and clock disabling for simultaneous test time and power reduction. od Jih-Jeen Chen

    Članak

    Test pattern generation and clock disabling for simultaneous test time and power reduction.
  3. 3

    Design-for-testability and fault-tolerant techniques for FFT processors. od Shyue-Kung Lu

    Članak

    Design-for-testability and fault-tolerant techniques for FFT processors.
  4. 4

    Test data compression technique for embedded cores using virtual scan chains. od Jas, A.

    Članak

    Test data compression technique for embedded cores using virtual scan chains.
  5. 5

    Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations. od Qikai Chen

    Članak

    Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations.
  6. 6

    Layout driven synthesis of multiple scan chains. od Rahimi, K.

    Članak

    Layout driven synthesis of multiple scan chains.
  7. 7

    Testing ASICs with multiple identical cores. od Yuejian Wu

    Članak

    Testing ASICs with multiple identical cores.
  8. 8

    Handling the pin overhead problem of DFTs for high-quality and at-speed tests. od Dong Xiang

    Članak

    Handling the pin overhead problem of DFTs for high-quality and at-speed tests.
  9. 9

    Autoscan a scan design without external scan inputs or outputs. od Pomeranz, I.

    Članak

    Autoscan a scan design without external scan inputs or outputs.
  10. 10

    Design-for-testability for embedded delay-locked loops. od Egan, T.

    Članak

    Design-for-testability for embedded delay-locked loops.

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