Εμφανίζονται 1 - 10 Αποτελέσματα από 10 για την αναζήτηση '"Design for testability."', χρόνος αναζήτησης: 0,02δλ Περιορισμός αποτελεσμάτων
  1. 1

    Testing big chips becomes an internal affair. ανά Runyon, S.

    Τόπος έκδοσης IEEE spectrum
    Άρθρο

    Testing big chips becomes an internal affair.
  2. 2

    Test pattern generation and clock disabling for simultaneous test time and power reduction. ανά Jih-Jeen Chen

    Άρθρο

    Test pattern generation and clock disabling for simultaneous test time and power reduction.
  3. 3

    Design-for-testability and fault-tolerant techniques for FFT processors. ανά Shyue-Kung Lu

    Τόπος έκδοσης IEEE Transactions on VLSI systems
    Άρθρο

    Design-for-testability and fault-tolerant techniques for FFT processors.
  4. 4

    Test data compression technique for embedded cores using virtual scan chains. ανά Jas, A.

    Τόπος έκδοσης IEEE Transactions on VLSI systems
    Άρθρο

    Test data compression technique for embedded cores using virtual scan chains.
  5. 5

    Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations. ανά Qikai Chen

    Τόπος έκδοσης IEEE Transactions on VLSI systems
    Άρθρο

    Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations.
  6. 6

    Layout driven synthesis of multiple scan chains. ανά Rahimi, K.

    Άρθρο

    Layout driven synthesis of multiple scan chains.
  7. 7

    Testing ASICs with multiple identical cores. ανά Yuejian Wu

    Άρθρο

    Testing ASICs with multiple identical cores.
  8. 8

    Handling the pin overhead problem of DFTs for high-quality and at-speed tests. ανά Dong Xiang

    Άρθρο

    Handling the pin overhead problem of DFTs for high-quality and at-speed tests.
  9. 9

    Autoscan a scan design without external scan inputs or outputs. ανά Pomeranz, I.

    Τόπος έκδοσης IEEE Transactions on VLSI systems
    Άρθρο

    Autoscan a scan design without external scan inputs or outputs.
  10. 10

    Design-for-testability for embedded delay-locked loops. ανά Egan, T.

    Τόπος έκδοσης IEEE Transactions on VLSI systems
    Άρθρο

    Design-for-testability for embedded delay-locked loops.

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