Zoekresultaten - "Design for testability."

1

Testing big chips becomes an internal affair. door Runyon, S.

Gepubliceerd in IEEE spectrum

Artikel

Testing big chips becomes an internal affair.

2

Test pattern generation and clock disabling for simultaneous test time and power reduction. door Jih-Jeen Chen

Gepubliceerd in IEEE Transactions on computer-aided design of integrated circuits and systems

Artikel

Test pattern generation and clock disabling for simultaneous test time and power reduction.

3

Design-for-testability and fault-tolerant techniques for FFT processors. door Shyue-Kung Lu

Gepubliceerd in IEEE Transactions on VLSI systems

Artikel

Design-for-testability and fault-tolerant techniques for FFT processors.

4

Test data compression technique for embedded cores using virtual scan chains. door Jas, A.

Gepubliceerd in IEEE Transactions on VLSI systems

Artikel

Test data compression technique for embedded cores using virtual scan chains.

5

Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations. door Qikai Chen

Gepubliceerd in IEEE Transactions on VLSI systems

Artikel

Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations.

6

Layout driven synthesis of multiple scan chains. door Rahimi, K.

Gepubliceerd in IEEE Transactions on computer-aided design of integrated circuits and systems

Artikel

Layout driven synthesis of multiple scan chains.

7

Testing ASICs with multiple identical cores. door Yuejian Wu

Gepubliceerd in IEEE Transactions on computer-aided design of integrated circuits and systems

Artikel

Testing ASICs with multiple identical cores.

8

Handling the pin overhead problem of DFTs for high-quality and at-speed tests. door Dong Xiang

Gepubliceerd in IEEE Transactions on computer-aided design of integrated circuits and systems

Artikel

Handling the pin overhead problem of DFTs for high-quality and at-speed tests.

9

Autoscan a scan design without external scan inputs or outputs. door Pomeranz, I.

Gepubliceerd in IEEE Transactions on VLSI systems

Artikel

Autoscan a scan design without external scan inputs or outputs.

10

Design-for-testability for embedded delay-locked loops. door Egan, T.

Gepubliceerd in IEEE Transactions on VLSI systems

Artikel

Testing big chips becomes an internal affair. door Runyon, S.

Test pattern generation and clock disabling for simultaneous test time and power reduction. door Jih-Jeen Chen

Design-for-testability and fault-tolerant techniques for FFT processors. door Shyue-Kung Lu

Test data compression technique for embedded cores using virtual scan chains. door Jas, A.

Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations. door Qikai Chen

Layout driven synthesis of multiple scan chains. door Rahimi, K.

Testing ASICs with multiple identical cores. door Yuejian Wu

Handling the pin overhead problem of DFTs for high-quality and at-speed tests. door Dong Xiang

Autoscan a scan design without external scan inputs or outputs. door Pomeranz, I.

Design-for-testability for embedded delay-locked loops. door Egan, T.

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