Dangos 81 - 90 canlyniadau o 136 ar gyfer chwilio '"Decoding."', amser ymholiad: 0.02e Mireinio'r Canlyniadau
  1. 81

    Fast factorization architecture in soft-decision Reed-Solomon decoding. gan Xinmiao Zhang

    Erthygl

    Fast factorization architecture in soft-decision Reed-Solomon decoding.
  2. 82

    Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders. gan Dobkin, R.

    Erthygl

    Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders.
  3. 83

    VLSI architectural design tradeoffs for sliding-window log-MAP decoders. gan Chien-Ming Wu

    Erthygl

    VLSI architectural design tradeoffs for sliding-window log-MAP decoders.
  4. 84

    A reconfigurable, power-efficient adaptive Viterbi decoder. gan Tessier, R.

    Erthygl

    A reconfigurable, power-efficient adaptive Viterbi decoder.
  5. 85

    Memory sub-banking scheme for high throughput MAP-based SISO decoders. gan Tiwari, M.

    Erthygl

    Memory sub-banking scheme for high throughput MAP-based SISO decoders.
  6. 86

    Speech recognition and utterance verification based on a generalized confidence score. gan Myoung-Wan Koo

    Erthygl

    Speech recognition and utterance verification based on a generalized confidence score.
  7. 87

    Softbit speech decoding a new approach to error concealment. gan Fingscheidt, T.

    Erthygl

    Softbit speech decoding a new approach to error concealment.
  8. 88

    Extending orthogonal block codes with partial feedback. gan Akhtar, J.

    Erthygl

    Extending orthogonal block codes with partial feedback.
  9. 89

    Parallel high-throughput limited search trellis decoder VLSI design. gan Fei Sun

    Erthygl

    Parallel high-throughput limited search trellis decoder VLSI design.
  10. 90

    A joint performance measure for the decorrelating multiuser detector. gan Nigam, I.

    Erthygl

    A joint performance measure for the decorrelating multiuser detector.

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