Showing 12,451 - 12,460 results of 13,059 for search '"Controller."', query time: 0.05s Refine Results
  1. 12451

    A 610-mW zero-overhead class-G full-rate ADSL CO line driver. by Maclean, K.

    Article

    A 610-mW zero-overhead class-G full-rate ADSL CO line driver.
  2. 12452

    A 402-output TFT-LCD driver IC with power control based on the number of colors selected. by Itakura, T.

    Article

    A 402-output TFT-LCD driver IC with power control based on the number of colors selected.
  3. 12453

    Performance-optimized microstrip coupled VCOs for 40-GHz and 43-GHz OC-768 optical transmission. by Shaeffer, D.K

    Article

    Performance-optimized microstrip coupled VCOs for 40-GHz and 43-GHz OC-768 optical transmission.
  4. 12454

    MOS varactors with n- and p-type gates and their influence on an LC-VCO in digital CMOS. by Maget, J.

    Article

    MOS varactors with n- and p-type gates and their influence on an LC-VCO in digital CMOS.
  5. 12455

    X.500 and LDAP security a comparative overview. by Hassler, V.

    Article

    X.500 and LDAP security a comparative overview.
  6. 12456

    A low-jitter mutual-correlated pulsewidth control loop circuit. by Wei-Ming Lin

    Article

    A low-jitter mutual-correlated pulsewidth control loop circuit.
  7. 12457

    A self-tuning DVS processor using delay-error detection and correction. by Das, S.

    Article

    A self-tuning DVS processor using delay-error detection and correction.
  8. 12458

    Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modes. by Nomura, M.

    Article

    Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modes.
  9. 12459

    A low leakage SRAM macro with replica cell biasing scheme. by Takeyama, Y.

    Article

    A low leakage SRAM macro with replica cell biasing scheme.
  10. 12460

    A 512-mb DDR3 SDRAM prototype with CIO minimization and self-calibration techniques. by Churoo Park

    Article

    A 512-mb DDR3 SDRAM prototype with CIO minimization and self-calibration techniques.

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