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Logic synthesis and SOC prototyping RTL design using VHDL
Publicerad 2020Available for University of the Philippines Diliman via SpringerLink. Click here to access
Also available remotely for University of the Philippines Diliman via SpringerLink. Click here to access thru EZproxy
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P63-M Isabela flood control project halfway complete. IN Provincial News
I publikationen Manila BulletinHämta fulltext
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Iteration abstraction in Sather.
I publikationen ACM transactions on programming languages and systems.Artikel -
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6 flood-control structures for Zamboanga Sibugay. IN Provincial News
I publikationen Manila BulletinHämta fulltext
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