Отображение 271 - 280 результаты of 283 для поиска '"Computer architectures."', время запроса: 0.03сек. Отмена результатов
  1. 271

    PROJECTION algorithm for motif finding on GPUs по Clemente, Jhoirene B.

    Analytics

    PROJECTION algorithm for motif finding on GPUs
  2. 272

    Journal of systems architecture.

    Continuing Resource

    Journal of systems architecture.
  3. 273

    Optimal broadcasting in the back to back d-ary trees. по Barth, Dominique

    Опубликовано в: Information processing letters.
    Статья

    Optimal broadcasting in the back to back d-ary trees.
  4. 274

    Implementation of a 32-bit dual core ARM7 microprocessor with split-private level one cache and shared level two data cache по Alidio, Lianne

    Диссертация

    Implementation of a 32-bit dual core ARM7 microprocessor with split-private level one cache and shared level two data cache
  5. 275

    High-Level Implementation of the 5-Stage Pipelined ARM9TDM Core по Arandilla, Christiensen dela Cruz

    Диссертация

    High-Level Implementation of the 5-Stage Pipelined ARM9TDM Core
  6. 276

    Multistage Switching Architectures for Software Routers. по Bianco, A.

    Статья

    Multistage Switching Architectures for Software Routers.
  7. 277

    Routability checking for three-dimensional architectures. по Hung, W.N.N

    Опубликовано в: IEEE Transactions on VLSI systems
    Статья

    Routability checking for three-dimensional architectures.
  8. 278

    Chip Design Hardwires Security. по Adee, S.

    Опубликовано в: IEEE spectrum
    Статья

    Chip Design Hardwires Security.
  9. 279

    Microarchitecture-level leakage reduction with data retention. по Weiping Liao

    Опубликовано в: IEEE Transactions on VLSI systems
    Статья

    Microarchitecture-level leakage reduction with data retention.
  10. 280

    Implementation of a 32-bit dual core ARM7 microprocessor with single level cache по Castro, Janelle Legaspi

    Диссертация

    Implementation of a 32-bit dual core ARM7 microprocessor with single level cache

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