Résultat(s) 511 - 520 résultats de 536 pour la requête '"Computer aided design."', Temps de recherche: 0,03s Affiner les résultats
  1. 511

    On the nonenumerative path delay fault simulation problem. par Kagaris, D.

    Article

    On the nonenumerative path delay fault simulation problem.
  2. 512

    Table look-up model of thin-film transistors for circuit simulation using spline interpolation with transformation by y x+log(x). par Kimura, M.

    Article

    Table look-up model of thin-film transistors for circuit simulation using spline interpolation with transformation by y x+log(x).
  3. 513

    Handling the pin overhead problem of DFTs for high-quality and at-speed tests. par Dong Xiang

    Article

    Handling the pin overhead problem of DFTs for high-quality and at-speed tests.
  4. 514

    Guest editor's introduction to special section on high-level design validation and test. par Karri, R.

    Article

    Guest editor's introduction to special section on high-level design validation and test.
  5. 515

    System-on-a-chip test-data compression and decompression architectures based on Golomb codes. par Chandra, A.

    Article

    System-on-a-chip test-data compression and decompression architectures based on Golomb codes.
  6. 516

    Software-based self-testing methodology for processor cores. par Li Chen

    Article

    Software-based self-testing methodology for processor cores.
  7. 517

    Using word-level ATPG and modular arithmetic constraint-solving techniques for assertion property checking. par Chung-Yang Huan

    Article

    Using word-level ATPG and modular arithmetic constraint-solving techniques for assertion property checking.
  8. 518

    Symbolic debugging of embedded hardware and software. par Koushanfar, F.

    Article

    Symbolic debugging of embedded hardware and software.
  9. 519

    Automatic test pattern generation for functional register-transfer level circuits using assignment decision diagrams. par Ghosh, I.

    Article

    Automatic test pattern generation for functional register-transfer level circuits using assignment decision diagrams.
  10. 520

    Path delay fault diagnosis and coverage-a metric and an estimation technique. par Sivaraman, M.

    Article

    Path delay fault diagnosis and coverage-a metric and an estimation technique.

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