Näytetään 201 - 210 yhteensä 244 tuloksesta haulle '"Circuits and systems."', hakuaika: 0,03s Tarkenna hakua
  1. 201

    Symbolic modeling of periodically time-varying systems using harmonic transfer matrices. Tekijä Vanassche, P.

    Artikkeli

    Symbolic modeling of periodically time-varying systems using harmonic transfer matrices.
  2. 202

    A timing-constrained simultaneous global routing algorithm. Tekijä Jiang Hu

    Artikkeli

    A timing-constrained simultaneous global routing algorithm.
  3. 203

    High-level energy macromodeling of embedded software. Tekijä Tat Kee Tan

    Artikkeli

    High-level energy macromodeling of embedded software.
  4. 204

    Value-sensitive automatic code specialization for embedded software. Tekijä Eui-Young Chung

    Artikkeli

    Value-sensitive automatic code specialization for embedded software.
  5. 205

    On the use of random limited-scan to improve at-speed random pattern testing of scan circuits. Tekijä Pomeranz, I.

    Artikkeli

    On the use of random limited-scan to improve at-speed random pattern testing of scan circuits.
  6. 206

    Algorithm level recomputing using allocation diversity a register transfer level approach to time redundancy-based concurrent error detection. Tekijä Kaijie Wu

    Artikkeli

    Algorithm level recomputing using allocation diversity a register transfer level approach to time redundancy-based concurrent error detection.
  7. 207

    System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints. Tekijä Iyengar, V.

    Artikkeli

    System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints.
  8. 208

    On the nonenumerative path delay fault simulation problem. Tekijä Kagaris, D.

    Artikkeli

    On the nonenumerative path delay fault simulation problem.
  9. 209

    Table look-up model of thin-film transistors for circuit simulation using spline interpolation with transformation by y x+log(x). Tekijä Kimura, M.

    Artikkeli

    Table look-up model of thin-film transistors for circuit simulation using spline interpolation with transformation by y x+log(x).
  10. 210

    Handling the pin overhead problem of DFTs for high-quality and at-speed tests. Tekijä Dong Xiang

    Artikkeli

    Handling the pin overhead problem of DFTs for high-quality and at-speed tests.

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