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2001
Efficient library characterization for high-level power estimation.
I publikationen IEEE Transactions on VLSI systemsArtikel -
2002
Modeling subthreshold SOI logic for static timing analysis.
I publikationen IEEE Transactions on VLSI systemsArtikel -
2003
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2004
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2005
Design of low-error fixed-width modified booth multiplier.
I publikationen IEEE Transactions on VLSI systemsArtikel -
2006
A new maximal diagnosis algorithm for interconnect test.
I publikationen IEEE Transactions on VLSI systemsArtikel -
2007
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2008
Scaling trends of on-chip power distribution noise.
I publikationen IEEE Transactions on VLSI systemsArtikel -
2009
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2010