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Modeling subthreshold SOI logic for static timing analysis.
I publikationen IEEE Transactions on VLSI systemsArtikel -
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Microarchitecture-level leakage reduction with data retention.
I publikationen IEEE Transactions on VLSI systemsArtikel -
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Equivalent circuit model of on-wafer CMOS interconnects for RFICs.
I publikationen IEEE Transactions on VLSI systemsArtikel