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A method for timing closure in supply voltage scaled CMOS digital circuits with dual-Vth devices
Cyhoeddwyd 2013Traethawd Ymchwil -
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Signal processing and integrated circuits
Cyhoeddwyd 2012Available for University of the Philippines Diliman via Wiley Online Library. Click here to access
Also available remotely for University of the Philippines Diliman via Wiley Online Library. Click here to access thru EZproxy
Electronic Resource -
85
Engineering the CMOS library enhancing digital design kits for competitive silicon
Cyhoeddwyd 2012Available for University of the Philippines Diliman via Wiley Online Library. Click here to access
Also available remotely for University of the Philippines Diliman via Wiley Online Library. Click here to access thru EZproxy
Electronic Resource -
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