Showing 11 - 20 results of 25 for search '"Chip design."', query time: 0.02s Refine Results
  1. 11

    A robust self-calibrating transmission scheme for on-chip networks. by Worm, F.

    Article

    A robust self-calibrating transmission scheme for on-chip networks.
  2. 12

    Baud-rate channel equalization in nanometer technologies. by Chou, E.Y

    Article

    Baud-rate channel equalization in nanometer technologies.
  3. 13

    Assessment of on-chip wire-length distribution models. by Lanzerotti, M.Y

    Article

    Assessment of on-chip wire-length distribution models.
  4. 14

    The secret art of chip graffiti. by Goldstein, H.

    Published in IEEE spectrum
    Article

    The secret art of chip graffiti.
  5. 15

    The secret art of chip graffiti. by Goldstein, H.

    Published in IEEE spectrum
    Article

    The secret art of chip graffiti.
  6. 16

    The secret art of chip graffiti. by Goldstein, H.

    Published in IEEE spectrum
    Article

    The secret art of chip graffiti.
  7. 17

    Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect. by Efthymiou, A.

    Article

    Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect.
  8. 18

    Chip Design Hardwires Security. by Adee, S.

    Published in IEEE spectrum
    Article

    Chip Design Hardwires Security.
  9. 19

    Chip Design Hardwires Security. by Adee, S.

    Published in IEEE spectrum
    Article

    Chip Design Hardwires Security.
  10. 20

    Sun's big splash [Niagara microprocessor chip]. by Geppert, L.

    Published in IEEE spectrum
    Article

    Sun's big splash [Niagara microprocessor chip].

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