Ngā hua rapu - "Capacitance."
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51
Switch-factor based loop RLC modeling for efficient timing analysis.
I whakaputaina i IEEE Transactions on VLSI systemsTuhinga -
52
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53
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54
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55
Design and application of CMOS bulk input scheme.
I whakaputaina i IEEE Journal of solid state circuitsTuhinga -
56
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57
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58
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59
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60