Showing 21 - 30 results of 59 for search '"Caching."', query time: 0.01s Refine Results
  1. 21

    A process-tolerant cache architecture for improved yield in nanoscale technologies. by Agarwal, A.

    Article

    A process-tolerant cache architecture for improved yield in nanoscale technologies.
  2. 22

    Zero-aware asymmetric SRAM cell for reducing cache power in writing zero. by Yen-Jen Chang

    Article

    Zero-aware asymmetric SRAM cell for reducing cache power in writing zero.
  3. 23

    DCG deterministic clock-gating for low-power microprocessor design. by Hai Li

    Article

    DCG deterministic clock-gating for low-power microprocessor design.
  4. 24

    Memory energy minimization by data compression algorithms, architectures and implementation. by Benini, L.

    Article

    Memory energy minimization by data compression algorithms, architectures and implementation.
  5. 25

    Adaptive power-aware prefetch in wireless networks. by Liangzhong Yin

    Article

    Adaptive power-aware prefetch in wireless networks.
  6. 26

    Runtime data sharing through an enterprise distributed cache. by Khan, Iqbal

    Published in MSDN magazine
    Article

    Runtime data sharing through an enterprise distributed cache.
  7. 27

    Address scalability bottlenecks with distributed caching. by Khan, Iqbal

    Published in MSDN magazine
    Article

    Address scalability bottlenecks with distributed caching.
  8. 28

    RISC maker. by Perry, T.S

    Published in IEEE spectrum
    Article

    RISC maker.
  9. 29

    RISC maker. by Perry, T.S

    Published in IEEE spectrum
    Article

    RISC maker.
  10. 30

    A study of cache sub-ranking and block buffering as power reduction techniques for multiprocessor cache design by Zarsuela, Jestoni V.

    Thesis

    A study of cache sub-ranking and block buffering as power reduction techniques for multiprocessor cache design

Search Tools: