Mostrando 11 - 20 Resultados de 20 Para Buscar '"Cache memory."', tiempo de consulta: 0.02s Limitar resultados
  1. 11

    RT-CaCC towards a cache-aware congestion control mechanism in wireless sensor networks por Alipio, Melchizedek I.

    Tesis

    RT-CaCC towards a cache-aware congestion control mechanism in wireless sensor networks
  2. 12

    Implementation of a 32-bit dual core ARM7 microprocessor with split-private level one cache and shared level two data cache por Alidio, Lianne

    Tesis

    Implementation of a 32-bit dual core ARM7 microprocessor with split-private level one cache and shared level two data cache
  3. 13

    Instruction code mapping for performance increase and energy reduction in embedded computer systems. por Parameswaran, S.

    Artículo

    Instruction code mapping for performance increase and energy reduction in embedded computer systems.
  4. 14

    A forward body-biased low-leakage SRAM cache device, circuit and architecture considerations. por Kim, C.H

    Artículo

    A forward body-biased low-leakage SRAM cache device, circuit and architecture considerations.
  5. 15

    Microarchitecture-level leakage reduction with data retention. por Weiping Liao

    Artículo

    Microarchitecture-level leakage reduction with data retention.
  6. 16

    Soft errors issues in low-power caches. por Degalahal, V.

    Artículo

    Soft errors issues in low-power caches.
  7. 17

    RISC maker. por Perry, T.S

    Publicado en IEEE spectrum
    Artículo

    RISC maker.
  8. 18

    Fast maximum intensity projections of large medical data sets by exploiting hierarchical memory architectures. por Kiefer, G.

    Artículo

    Fast maximum intensity projections of large medical data sets by exploiting hierarchical memory architectures.
  9. 19

    A Case for Asymmetric-Cell Cache Memories. por Moshovos, A.

    Artículo

    A Case for Asymmetric-Cell Cache Memories.
  10. 20

    Bounding cache-related preemption delay for real-time systems. por Chang-Gun Lee

    Artículo

    Bounding cache-related preemption delay for real-time systems.

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