A mostrar 11 - 20 resultados de 20 para a pesquisa '"Cache memory"', tempo de pesquisa: 0.02seg Refinar resultados
  1. 11

    RT-CaCC towards a cache-aware congestion control mechanism in wireless sensor networks Por Alipio, Melchizedek I.

    Thesis

    RT-CaCC towards a cache-aware congestion control mechanism in wireless sensor networks
  2. 12

    Implementation of a 32-bit dual core ARM7 microprocessor with split-private level one cache and shared level two data cache Por Alidio, Lianne

    Thesis

    Implementation of a 32-bit dual core ARM7 microprocessor with split-private level one cache and shared level two data cache
  3. 13

    Instruction code mapping for performance increase and energy reduction in embedded computer systems. Por Parameswaran, S.

    Artigo

    Instruction code mapping for performance increase and energy reduction in embedded computer systems.
  4. 14

    A forward body-biased low-leakage SRAM cache device, circuit and architecture considerations. Por Kim, C.H

    Artigo

    A forward body-biased low-leakage SRAM cache device, circuit and architecture considerations.
  5. 15

    Microarchitecture-level leakage reduction with data retention. Por Weiping Liao

    Artigo

    Microarchitecture-level leakage reduction with data retention.
  6. 16

    Soft errors issues in low-power caches. Por Degalahal, V.

    Artigo

    Soft errors issues in low-power caches.
  7. 17

    RISC maker. Por Perry, T.S

    Publicado no IEEE spectrum
    Artigo

    RISC maker.
  8. 18

    Fast maximum intensity projections of large medical data sets by exploiting hierarchical memory architectures. Por Kiefer, G.

    Artigo

    Fast maximum intensity projections of large medical data sets by exploiting hierarchical memory architectures.
  9. 19

    A Case for Asymmetric-Cell Cache Memories. Por Moshovos, A.

    Artigo

    A Case for Asymmetric-Cell Cache Memories.
  10. 20

    Bounding cache-related preemption delay for real-time systems. Por Chang-Gun Lee

    Artigo

    Bounding cache-related preemption delay for real-time systems.

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