Showing 231 - 240 results of 301 for search '"CMOS."', query time: 0.02s Refine Results
  1. 231

    A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor. by Khellah, M.

    Article

    A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor.
  2. 232

    The High-k Solution. by Bohr, M.T

    Published in IEEE spectrum
    Article

    The High-k Solution.
  3. 233

    VLSI implementation of a signal recognition and code acquisition algorithm for CDMA packet receivers. by Fanucci, L.

    Article

    VLSI implementation of a signal recognition and code acquisition algorithm for CDMA packet receivers.
  4. 234

    Through a lens sharply [FluidFocus lens]. by Hendriks, B.

    Published in IEEE spectrum
    Article

    Through a lens sharply [FluidFocus lens].
  5. 235

    A low-power DSP core-based software radio architecture. by Gunn, J.E

    Article

    A low-power DSP core-based software radio architecture.
  6. 236

    A review of 0.18-μm full adder performances for tree structured arithmetic circuits. by Chip-Hong Chang

    Article

    A review of 0.18-μm full adder performances for tree structured arithmetic circuits.
  7. 237

    A hardware-efficient technique to implement a trellis code modulation decoder. by Dinh, A.

    Article

    A hardware-efficient technique to implement a trellis code modulation decoder.
  8. 238

    Comparison of high-performance VLSI adders in the energy-delay space. by Oklobdzija, V.G

    Article

    Comparison of high-performance VLSI adders in the energy-delay space.
  9. 239

    Design and analysis of an ultrawide-band distributed CMOS mixer. by Safarian, A.Q

    Article

    Design and analysis of an ultrawide-band distributed CMOS mixer.
  10. 240

    A novel yield optimization technique for digital CMOS circuits design by means of process parameters run-time estimation and body bias active control. by Olivieri, M.

    Article

    A novel yield optimization technique for digital CMOS circuits design by means of process parameters run-time estimation and body bias active control.

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