Showing 1 - 10 results of 70 for search '"CMOS technology."', सवाल का समय: 0.02सेकंड परिणाम को परिष्कृत करें
  1. 1

    A single-chip storage LSI for home networks.

    में प्रकाशित IEEE Communications magazine
    लेख

    A single-chip storage LSI for home networks.
  2. 2

    A high-throughput low-cost AES processor. द्वारा Su, Chih-Pin

    में प्रकाशित IEEE Communications magazine
    लेख

    A high-throughput low-cost AES processor.
  3. 3

    Implantable biomimetic microelectronic systems design. द्वारा Wentai Liu

    में प्रकाशित IEEE Engineering in medicine and biology magazine
    लेख

    Implantable biomimetic microelectronic systems design.
  4. 4

    Low-voltage high-speed switched-capacitor circuits without voltage bootstrapper. द्वारा Lei Wang

    में प्रकाशित IEEE Journal of solid state circuits
    लेख

    Low-voltage high-speed switched-capacitor circuits without voltage bootstrapper.
  5. 5

    A 3.3-V ISDN U-interface line driver with a new IQ-control circuit. द्वारा Jinup Lim

    में प्रकाशित IEEE Journal of solid state circuits
    लेख

    A 3.3-V ISDN U-interface line driver with a new IQ-control circuit.
  6. 6

    A 40-GHz-bandwidth, 4-bit, time-interleaved A द्वारा Nathawad, L.Y

    में प्रकाशित IEEE Journal of solid state circuits
    लेख

    A 40-GHz-bandwidth, 4-bit, time-interleaved A
  7. 7

    Discrete-time parametric amplification based on a three-terminal MOS varactor analysis and experimental results. द्वारा Ranganathan, S.

    में प्रकाशित IEEE Journal of solid state circuits
    लेख

    Discrete-time parametric amplification based on a three-terminal MOS varactor analysis and experimental results.
  8. 8

    A 1-V transformer-feedback low-noise amplifier for 5-GHz wireless LAN in 0.18-μm CMOS. द्वारा Cassan, D.J

    में प्रकाशित IEEE Journal of solid state circuits
    लेख

    A 1-V transformer-feedback low-noise amplifier for 5-GHz wireless LAN in 0.18-μm CMOS.
  9. 9

    Process and circuit design interlock for application-dependent scaling tradeoffs and optimization in the SoC era. द्वारा Diaz, C.H

    में प्रकाशित IEEE Journal of solid state circuits
    लेख

    Process and circuit design interlock for application-dependent scaling tradeoffs and optimization in the SoC era.
  10. 10

    A single-chip digitally calibrated 5.15-5.825-GHz 0.18-μm CMOS transceiver for 802.11a wireless LAN. द्वारा Vassiliou, I.

    में प्रकाशित IEEE Journal of solid state circuits
    लेख

    A single-chip digitally calibrated 5.15-5.825-GHz 0.18-μm CMOS transceiver for 802.11a wireless LAN.

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