Showing 1 - 4 results of 4 for search '"CMOS standard cell."', זמן שאילתה: 0.02s Refine Results
  1. 1

    Area-efficient high-throughput MAP decoder architectures. מאת Seok-Jun Lee

    הוצא לאור ב IEEE Transactions on VLSI systems
    Article

    Area-efficient high-throughput MAP decoder architectures.
  2. 2

    Design and performance testing of a 2.29-GB מאת Verbauwhede, I.

    Article

    Design and performance testing of a 2.29-GB
  3. 3

    A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture. מאת Morioka, S.

    הוצא לאור ב IEEE Transactions on VLSI systems
    Article

    A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture.
  4. 4

    High-performance VLSI architecture of adaptive decision feedback equalizer based on predictive parallel branch slicer (PPBS) scheme. מאת Meng-Da Yang

    הוצא לאור ב IEEE Transactions on VLSI systems
    Article

    High-performance VLSI architecture of adaptive decision feedback equalizer based on predictive parallel branch slicer (PPBS) scheme.

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