Sökresultat - "CMOS process."

31

A micropower low-voltage multiplier with reduced spurious switching. av Kwen-Siong Chong

I publikationen IEEE Transactions on VLSI systems

Artikel

32

An AI-calibrated IF filter a yield enhancement method with area and power dissipation reductions. av Murakawa, M.

I publikationen IEEE Journal of solid state circuits

Artikel

33

A 2.2-mW CMOS bandpass continuous-time multibit Δ-Σ ADC with 68 dB of dynamic range and 1-MHz bandwidth for wireless applications. av Kappes, M.S

I publikationen IEEE Journal of solid state circuits

Artikel

34

Modeling of the bulk versus SOI CMOS performances for the optimal design of APS circuits in low-power low-voltage applications. av Afzalian, A.

I publikationen IEEE Transactions on electron devices

Artikel

35

Design on ESD protection scheme for IC with power-down-mode operation. av Ming-Dou Ker

I publikationen IEEE Journal of solid state circuits

Artikel

36

A 1.5-V 75-dB dynamic range third-order Gm-C filter integrated in a 0.18-μm standard digital CMOS process. av Yodprasit, U.

I publikationen IEEE Journal of solid state circuits

Artikel

37

High Voltage Tolerant Linear Regulator With Fast Digital Control for Biasing of Integrated DC-DC Converters. av Hazucha, P.

I publikationen IEEE Journal of solid state circuits

Artikel

38

SoC with an integrated DSP and a 2.4-GHz RF transmitter. av Staszewski, R.B

I publikationen IEEE Transactions on VLSI systems

Artikel

39

A jitter characterization system using a component-invariant Vernier delay line. av Chan, A.H

I publikationen IEEE Transactions on VLSI systems

Artikel

40

A review of 0.18-μm full adder performances for tree structured arithmetic circuits. av Chip-Hong Chang

I publikationen IEEE Transactions on VLSI systems

Artikel

Sökresultat - "CMOS process."

A micropower low-voltage multiplier with reduced spurious switching. av Kwen-Siong Chong

An AI-calibrated IF filter a yield enhancement method with area and power dissipation reductions. av Murakawa, M.

A 2.2-mW CMOS bandpass continuous-time multibit Δ-Σ ADC with 68 dB of dynamic range and 1-MHz bandwidth for wireless applications. av Kappes, M.S

Modeling of the bulk versus SOI CMOS performances for the optimal design of APS circuits in low-power low-voltage applications. av Afzalian, A.

Design on ESD protection scheme for IC with power-down-mode operation. av Ming-Dou Ker

A 1.5-V 75-dB dynamic range third-order Gm-C filter integrated in a 0.18-μm standard digital CMOS process. av Yodprasit, U.

High Voltage Tolerant Linear Regulator With Fast Digital Control for Biasing of Integrated DC-DC Converters. av Hazucha, P.

SoC with an integrated DSP and a 2.4-GHz RF transmitter. av Staszewski, R.B

A jitter characterization system using a component-invariant Vernier delay line. av Chan, A.H

A review of 0.18-μm full adder performances for tree structured arithmetic circuits. av Chip-Hong Chang

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