Search Results - "CMOS process."

11

A 2.2-mW CMOS bandpass continuous-time multibit Δ-Σ ADC with 68 dB of dynamic range and 1-MHz bandwidth for wireless applications. by Kappes, M.S

Published in IEEE Journal of solid state circuits

Article

A 2.2-mW CMOS bandpass continuous-time multibit Δ-Σ ADC with 68 dB of dynamic range and 1-MHz bandwidth for wireless applications.

12

Design and implementation of pipelined analog-to-digital converters in a 90nm CMOS process by Dizon, Aaron Galvez

Thesis

13

Metal-mask configurable RF front-end circuits. by Yang Xu

Published in IEEE Journal of solid state circuits

Article

Metal-mask configurable RF front-end circuits.

14

A 21.5 by Mingquan Bao

Published in IEEE Journal of solid state circuits

Article

15

A 20-GHz phase-locked loop for 40-gb by Jaeha Kim

Published in IEEE Journal of solid state circuits

Article

16

A multi-rate 9.953-12.5-GHz 0.2-μm SiGe BiCMOS LC oscillator using a resistor-tuned varactor and a supply pushing cancellation circuit. by Maxim, A.

Published in IEEE Journal of solid state circuits

Article

A multi-rate 9.953-12.5-GHz 0.2-μm SiGe BiCMOS LC oscillator using a resistor-tuned varactor and a supply pushing cancellation circuit.

17

A 0.13 μm CMOS front-end, for DCS1800/UMTS by Liscidini, A.

Published in IEEE Journal of solid state circuits

Article

A 0.13 μm CMOS front-end, for DCS1800/UMTS

18

Pulse-width modulation pre-emphasis applied in a wireline transmitter, achieving 33 dB loss compensation at 5-Gb by Schrader, J.-R

Published in IEEE Journal of solid state circuits

Article

Pulse-width modulation pre-emphasis applied in a wireline transmitter, achieving 33 dB loss compensation at 5-Gb

19

A CAD methodology for optimizing transistor current and sizing in analog CMOS design. by Binkley, D.M

Published in IEEE Transactions on computer-aided design of integrated circuits and systems

Article

A CAD methodology for optimizing transistor current and sizing in analog CMOS design.

20

Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-μm CMOS process. by Ming-Dou Ker

Published in IEEE Transactions on electron devices

Article

A 2.2-mW CMOS bandpass continuous-time multibit Δ-Σ ADC with 68 dB of dynamic range and 1-MHz bandwidth for wireless applications. by Kappes, M.S

Design and implementation of pipelined analog-to-digital converters in a 90nm CMOS process by Dizon, Aaron Galvez

Metal-mask configurable RF front-end circuits. by Yang Xu

A 21.5 by Mingquan Bao

A 20-GHz phase-locked loop for 40-gb by Jaeha Kim

A multi-rate 9.953-12.5-GHz 0.2-μm SiGe BiCMOS LC oscillator using a resistor-tuned varactor and a supply pushing cancellation circuit. by Maxim, A.

A 0.13 μm CMOS front-end, for DCS1800/UMTS by Liscidini, A.

Pulse-width modulation pre-emphasis applied in a wireline transmitter, achieving 33 dB loss compensation at 5-Gb by Schrader, J.-R

A CAD methodology for optimizing transistor current and sizing in analog CMOS design. by Binkley, D.M

Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-μm CMOS process. by Ming-Dou Ker

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