Search Results - "CMOS process."

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  1. 11

    A novel yield optimization technique for digital CMOS circuits design by means of process parameters run-time estimation and body bias active control. by Olivieri, M.

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  2. 12

    A sensitivity and linearity improvement of a 100-dB dynamic range CMOS image sensor using a lateral overflow integration capacitor. by Akahane, N.

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  3. 13

    Low-power on-chip communication based on transition-aware global signaling (TAGS). by Kaul, H.

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  4. 14

    Energy-Efficient GHz-Class Charge-Recovery Logic. by Sathe, V. S.

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  5. 15

    Automatic phase alignment for a fully integrated Cartesian feedback power amplifier system. by Dawson, J.L

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  6. 16

    A slew-rate controlled output driver using PLL as compensation circuit. by Soon-Kyun Shin

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  7. 17

    Pulsed current-mode signaling for nearly speed-of-light intrachip communication. by Jose, A.P

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  8. 18

    A 1.4-V 10-bit 25-MS by Dong-Young Chang

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  9. 19

    A 20-GHz phase-locked loop for 40-gb by Jaeha Kim

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  10. 20

    Circuit and microarchitectural techniques for reducing cache leakage power. by Nam Sung Kim

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