Search Results - "CMOS circuit."

11

A novel yield optimization technique for digital CMOS circuits design by means of process parameters run-time estimation and body bias active control. by Olivieri, M.

Published in IEEE Transactions on VLSI systems

Article

A novel yield optimization technique for digital CMOS circuits design by means of process parameters run-time estimation and body bias active control.

12

A novel wavelet transform-based transient current analysis for fault detection and localization. by Bhunia, S.

Published in IEEE Transactions on VLSI systems

Article

A novel wavelet transform-based transient current analysis for fault detection and localization.

13

Design of wireless on-wafer submicron characterization system. by Moore, B.

Published in IEEE Transactions on VLSI systems

Article

Design of wireless on-wafer submicron characterization system.

14

Efficient algorithms for multilevel power estimation of VLSI circuits. by Bachmann, W.W

Published in IEEE Transactions on VLSI systems

Article

Efficient algorithms for multilevel power estimation of VLSI circuits.

15

Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations. by Qikai Chen

Published in IEEE Transactions on VLSI systems

Article

Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations.

16

Supertubes [carbon nanotubes]. by Avouris, P.

Published in IEEE spectrum

Article

17

A better bipolar transistor for wireless ICs. by Geppert, L.

Published in IEEE spectrum

Article

A better bipolar transistor for wireless ICs.

18

Methods for minimizing dynamic power consumption in synchronous designs with multiple supply voltages. by Chabini, N.

Published in IEEE Transactions on computer-aided design of integrated circuits and systems

Article

Methods for minimizing dynamic power consumption in synchronous designs with multiple supply voltages.

19

CMOS circuit verification with symbolic switch-level timing simulation. by McDonald, C.B

Published in IEEE Transactions on computer-aided design of integrated circuits and systems

Article

CMOS circuit verification with symbolic switch-level timing simulation.

20

A framework for energy and transient power reduction during behavioral synthesis. by Mohanty, S.P

Published in IEEE Transactions on VLSI systems

Article

A novel yield optimization technique for digital CMOS circuits design by means of process parameters run-time estimation and body bias active control. by Olivieri, M.

A novel wavelet transform-based transient current analysis for fault detection and localization. by Bhunia, S.

Design of wireless on-wafer submicron characterization system. by Moore, B.

Efficient algorithms for multilevel power estimation of VLSI circuits. by Bachmann, W.W

Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations. by Qikai Chen

Supertubes [carbon nanotubes]. by Avouris, P.

A better bipolar transistor for wireless ICs. by Geppert, L.

Methods for minimizing dynamic power consumption in synchronous designs with multiple supply voltages. by Chabini, N.

CMOS circuit verification with symbolic switch-level timing simulation. by McDonald, C.B

A framework for energy and transient power reduction during behavioral synthesis. by Mohanty, S.P

Search Tools:

Refine Results

DATABASE

AUTHOR

RESOURCE TYPE

LANGUAGE