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  1. 1

    A new queuing strategy for large scale ATM switches. per Guizani, M.

    Article

    A new queuing strategy for large scale ATM switches.
  2. 2

    A study of cache sub-ranking and block buffering as power reduction techniques for multiprocessor cache design per Zarsuela, Jestoni V.

    Thesis

    A study of cache sub-ranking and block buffering as power reduction techniques for multiprocessor cache design

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