Search Results - "Benchmark."

141

Efficient algorithms for multilevel power estimation of VLSI circuits. by Bachmann, W.W

Published in IEEE Transactions on VLSI systems

Article

Efficient algorithms for multilevel power estimation of VLSI circuits.

142

Sequence-switch coding for low-power data transmission. by Myungchul Yoon

Published in IEEE Transactions on VLSI systems

Article

Sequence-switch coding for low-power data transmission.

143

Placement constraints in floorplan design. by Young, E.F.Y

Published in IEEE Transactions on VLSI systems

Article

Placement constraints in floorplan design.

144

Tight integration of timing-driven synthesis and placement of parallel multiplier circuits. by Shin, K.

Published in IEEE Transactions on VLSI systems

Article

Tight integration of timing-driven synthesis and placement of parallel multiplier circuits.

145

Power minimization in QoS sensitive systems. by Wong, J.L

Published in IEEE Transactions on VLSI systems

Article

Power minimization in QoS sensitive systems.

146

Overview of a compiler for synthesizing MATLAB programs onto FPGAs. by Banerjee, P.

Published in IEEE Transactions on VLSI systems

Article

Overview of a compiler for synthesizing MATLAB programs onto FPGAs.

147

On-chip traffic modeling and synthesis for MPEG-2 video applications. by Varatkar, G.V

Published in IEEE Transactions on VLSI systems

Article

On-chip traffic modeling and synthesis for MPEG-2 video applications.

148

Note on generalization in experimental algorithmics. by Ramakrishnan, Naren

Published in ACM transactions on mathematical software.

Article

Note on generalization in experimental algorithmics.

149

Automatic interconnection rectification for SoC design verification based on the port order fault model. by Chun-Yao Wang

Published in IEEE Transactions on computer-aided design of integrated circuits and systems

Article

Automatic interconnection rectification for SoC design verification based on the port order fault model.

150

A timing-constrained simultaneous global routing algorithm. by Jiang Hu

Published in IEEE Transactions on computer-aided design of integrated circuits and systems

Article

Efficient algorithms for multilevel power estimation of VLSI circuits. by Bachmann, W.W

Sequence-switch coding for low-power data transmission. by Myungchul Yoon

Placement constraints in floorplan design. by Young, E.F.Y

Tight integration of timing-driven synthesis and placement of parallel multiplier circuits. by Shin, K.

Power minimization in QoS sensitive systems. by Wong, J.L

Overview of a compiler for synthesizing MATLAB programs onto FPGAs. by Banerjee, P.

On-chip traffic modeling and synthesis for MPEG-2 video applications. by Varatkar, G.V

Note on generalization in experimental algorithmics. by Ramakrishnan, Naren

Automatic interconnection rectification for SoC design verification based on the port order fault model. by Chun-Yao Wang

A timing-constrained simultaneous global routing algorithm. by Jiang Hu

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