Showing 1 - 10 results of 19 for search '"Benchmark circuits."', query time: 0.02s Refine Results
  1. 1

    A novel FPGA architecture supporting wide, shallow memories. by Oldridge, S.W

    Article

    A novel FPGA architecture supporting wide, shallow memories.
  2. 2

    Multimode power modeling and maximum-likelihood estimation. by Chandramouli, R.

    Article

    Multimode power modeling and maximum-likelihood estimation.
  3. 3

    High performance level conversion for dual VDD design. by Kulkarni, S.H

    Article

    High performance level conversion for dual VDD design.
  4. 4

    Efficient library characterization for high-level power estimation. by Dhaou, I.B

    Article

    Efficient library characterization for high-level power estimation.
  5. 5

    The effect of LUT and cluster size on deep-submicron FPGA performance and density. by Ahmed, E.

    Article

    The effect of LUT and cluster size on deep-submicron FPGA performance and density.
  6. 6

    Diagnosis of single stuck-at faults and multiple timing faults in scan chains. by Chien-Mo Li, J.

    Article

    Diagnosis of single stuck-at faults and multiple timing faults in scan chains.
  7. 7

    An efficient merging scheme for prescribed skew clock routing. by Chaturvedi, R.

    Article

    An efficient merging scheme for prescribed skew clock routing.
  8. 8

    POMR a power-aware interconnect optimization methodology. by Youssef, A.

    Article

    POMR a power-aware interconnect optimization methodology.
  9. 9

    Efficient algorithms for multilevel power estimation of VLSI circuits. by Bachmann, W.W

    Article

    Efficient algorithms for multilevel power estimation of VLSI circuits.
  10. 10

    A timing-constrained simultaneous global routing algorithm. by Jiang Hu

    Article

    A timing-constrained simultaneous global routing algorithm.

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