Showing 1 - 8 results of 8 for search '"BIST."', query time: 0.01s Refine Results
  1. 1

    Test pattern generation and clock disabling for simultaneous test time and power reduction. by Jih-Jeen Chen

    Article

    Test pattern generation and clock disabling for simultaneous test time and power reduction.
  2. 2

    Weighted pseudorandom hybrid BIST. by Jas, A.

    Article

    Weighted pseudorandom hybrid BIST.
  3. 3

    Online BIST and BIST-based diagnosis of FPGA logic blocks. by Abramovici, M.

    Article

    Online BIST and BIST-based diagnosis of FPGA logic blocks.
  4. 4

    Testing ASICs with multiple identical cores. by Yuejian Wu

    Article

    Testing ASICs with multiple identical cores.
  5. 5

    Design of hierarchical cellular automata for on-chip test pattern generator. by Sikdar, B.K

    Article

    Design of hierarchical cellular automata for on-chip test pattern generator.
  6. 6

    Handling the pin overhead problem of DFTs for high-quality and at-speed tests. by Dong Xiang

    Article

    Handling the pin overhead problem of DFTs for high-quality and at-speed tests.
  7. 7

    Software-based self-testing methodology for processor cores. by Li Chen

    Article

    Software-based self-testing methodology for processor cores.
  8. 8

    Design and analysis of compact dictionaries for diagnosis in scan-BIST. by Chunsheng Liu

    Article

    Design and analysis of compact dictionaries for diagnosis in scan-BIST.

Search Tools: