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Testing big chips becomes an internal affair.
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Runyon, S.
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IEEE spectrum
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Diagnosis of single stuck-at faults and multiple timing faults in scan chains.
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Chien-Mo Li, J.
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IEEE Transactions on VLSI systems
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Function-based compact test pattern generation for path delay faults.
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Michael, M.K
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On the nonenumerative path delay fault simulation problem.
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Kagaris, D.
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IEEE Transactions on computer-aided design of integrated circuits and systems
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Automatic test pattern generation for functional register-transfer level circuits using assignment decision diagrams.
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Ghosh, I.
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IEEE Transactions on computer-aided design of integrated circuits and systems
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DATABASE
Union Catalog (Buklod)
5 results
5
AUTHOR
Chien-Mo Li, J.
1 results
1
Ghosh, I.
1 results
1
Kagaris, D.
1 results
1
Michael, M.K
1 results
1
Runyon, S.
1 results
1
RESOURCE TYPE
Article
5 results
5
LANGUAGE
English
5 results
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