Prikaz rezultata 1 – 5 od 5 za pretragu '"Automatic test pattern generation."', vrijeme upita: 0,02s Detaljiziraj rezultate
  1. 1

    Testing big chips becomes an internal affair. od Runyon, S.

    Izdano u IEEE spectrum
    Članak

    Testing big chips becomes an internal affair.
  2. 2

    Diagnosis of single stuck-at faults and multiple timing faults in scan chains. od Chien-Mo Li, J.

    Članak

    Diagnosis of single stuck-at faults and multiple timing faults in scan chains.
  3. 3

    Function-based compact test pattern generation for path delay faults. od Michael, M.K

    Članak

    Function-based compact test pattern generation for path delay faults.
  4. 4

    On the nonenumerative path delay fault simulation problem. od Kagaris, D.

    Članak

    On the nonenumerative path delay fault simulation problem.
  5. 5

    Automatic test pattern generation for functional register-transfer level circuits using assignment decision diagrams. od Ghosh, I.

    Članak

    Automatic test pattern generation for functional register-transfer level circuits using assignment decision diagrams.

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