Sökresultat - "Architecture"

7701

Weighted pseudorandom hybrid BIST. av Jas, A.

I publikationen IEEE Transactions on VLSI systems

Artikel

7702

Near-linear CMOS I av Esch, G., Jr

I publikationen IEEE Transactions on VLSI systems

Artikel

7703

Power estimation techniques for FPGAs. av Anderson, J.H

I publikationen IEEE Transactions on VLSI systems

Artikel

7704

Design of ultrahigh-speed low-voltage CMOS CML buffers and latches. av Heydari, P.

I publikationen IEEE Transactions on VLSI systems

Artikel

Design of ultrahigh-speed low-voltage CMOS CML buffers and latches.

7705

Highly efficient, limited range multipliers for LUT-based FPGA architectures. av Turner, R.H

I publikationen IEEE Transactions on VLSI systems

Artikel

Highly efficient, limited range multipliers for LUT-based FPGA architectures.

7706

Combining a performance estimation methodology with a hardware av Baghdadi, A.

I publikationen IEEE Transactions on software engineering

Artikel

Combining a performance estimation methodology with a hardware

7707

Virtual benchmarking and model continuity in prototyping embedded multiprocessor signal processing systems. av Janka, R.S

I publikationen IEEE Transactions on software engineering

Artikel

Virtual benchmarking and model continuity in prototyping embedded multiprocessor signal processing systems.

7708

High-speed VLSI architectures for the AES algorithm. av Xinmiao Zhang

I publikationen IEEE Transactions on VLSI systems

Artikel

High-speed VLSI architectures for the AES algorithm.

7709

Zero-aware asymmetric SRAM cell for reducing cache power in writing zero. av Yen-Jen Chang

I publikationen IEEE Transactions on VLSI systems

Artikel

Zero-aware asymmetric SRAM cell for reducing cache power in writing zero.

7710

A survey of mobility management in next-generation all-IP-based wireless systems. av Akyildiz, I.F

I publikationen IEEE Wireless communications

Artikel

Weighted pseudorandom hybrid BIST. av Jas, A.

Near-linear CMOS I av Esch, G., Jr

Power estimation techniques for FPGAs. av Anderson, J.H

Design of ultrahigh-speed low-voltage CMOS CML buffers and latches. av Heydari, P.

Highly efficient, limited range multipliers for LUT-based FPGA architectures. av Turner, R.H

Combining a performance estimation methodology with a hardware av Baghdadi, A.

Virtual benchmarking and model continuity in prototyping embedded multiprocessor signal processing systems. av Janka, R.S

High-speed VLSI architectures for the AES algorithm. av Xinmiao Zhang

Zero-aware asymmetric SRAM cell for reducing cache power in writing zero. av Yen-Jen Chang

A survey of mobility management in next-generation all-IP-based wireless systems. av Akyildiz, I.F

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