ASIC design and synthesis RTL design using Verilog por Taraate, Vaibbhav

Also available remotely for the University of the Philippines System via SpringerLink. Click here to access thru EZproxy
Available for University of the Philippines System via SpringerLink. Click here to access

ASIC/SoC functional design verification a comprehensive guide to technologies and methodologies por Mehta, Ashok B.

Available for University of the Philippines System via SpringerLink. Click here to access
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PLD based design with VHDL RTL design, synthesis and implementation por Taraate, Vaibbhav

Available for University of the Philippines Diliman via SpringerLink. Click here to access
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Model generation in electronic design

Logic design for array-based circuits a structured design methodology por White, Donnamaie E. 1942-

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Successful ASIC design the first time through por Huber, John P.