Search Results - "Advanced Encryption Standards."

1

A high-throughput low-cost AES processor. by Su, Chih-Pin

Published in IEEE Communications magazine

Article

A high-throughput low-cost AES processor.

2

Concurrent error detection schemes for fault-based side-channel cryptanalysis of symmetric block ciphers. by Karri, R.

Published in IEEE Transactions on computer-aided design of integrated circuits and systems

Article

Concurrent error detection schemes for fault-based side-channel cryptanalysis of symmetric block ciphers.

3

High-speed VLSI architectures for the AES algorithm. by Xinmiao Zhang

Published in IEEE Transactions on VLSI systems

Article

High-speed VLSI architectures for the AES algorithm.

4

Secure mobile medical record system for tuberculosis using public key infrastructure and selective encryption of medical images (SuMMeRS) by Roque, Jonas Fabian

Thesis

5

Design and performance testing of a 2.29-GB by Verbauwhede, I.

Published in IEEE Journal of solid state circuits

Article

Design and performance testing of a 2.29-GB

6

AES-Based Security Coprocessor IC in 0.18- \mu\hbox {m} CMOS With Resistance to Differential Power Analysis Side-Channel Attacks. by Hwang, D.D

Published in IEEE Journal of solid state circuits

Article

$AES-Based Security Coprocessor IC in 0.18- \mu\hbox {m} CMOS With Resistance to Differential Power Analysis Side-Channel Attacks.$

7

InvMixColumn decomposition and multilevel resource sharing in AES implementations. by Fischer, V.

Published in IEEE Transactions on VLSI systems

Article

InvMixColumn decomposition and multilevel resource sharing in AES implementations.

8

DVD copy protection take 2. by Perry, T.S

Published in IEEE spectrum

Article

9

A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture. by Morioka, S.

Published in IEEE Transactions on VLSI systems

Article

A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture.

10

A note on the fragility of the "Michael" message integrity code. by Wool, A.

Published in IEEE Transactions on wireless communications

Article

A high-throughput low-cost AES processor. by Su, Chih-Pin

Concurrent error detection schemes for fault-based side-channel cryptanalysis of symmetric block ciphers. by Karri, R.

High-speed VLSI architectures for the AES algorithm. by Xinmiao Zhang

Secure mobile medical record system for tuberculosis using public key infrastructure and selective encryption of medical images (SuMMeRS) by Roque, Jonas Fabian

Design and performance testing of a 2.29-GB by Verbauwhede, I.

AES-Based Security Coprocessor IC in 0.18- \mu\hbox {m} CMOS With Resistance to Differential Power Analysis Side-Channel Attacks. by Hwang, D.D

InvMixColumn decomposition and multilevel resource sharing in AES implementations. by Fischer, V.

DVD copy protection take 2. by Perry, T.S

A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture. by Morioka, S.

A note on the fragility of the "Michael" message integrity code. by Wool, A.

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