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On the impact of on-chip inductance on signal nets under the influence of power grid noise.
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Utilizing the effect of relative delay on energy dissipation in low-power on-chip buses.
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An architecture and compiler for scalable on-chip communication.
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A jitter characterization system using a component-invariant Vernier delay line.
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Early probabilistic noise estimation for capacitively coupled interconnects.
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Power complexity of multiplexer-based optoelectronic crossbar switches.
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Equivalent circuit model of on-wafer CMOS interconnects for RFICs.
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DATABASE
Union Catalog (Buklod)
57 results
57
AUTHOR
Analui, B.
1 results
1
Becer, M.R
1 results
1
Borgatti, M.
1 results
1
Casper, B.
1 results
1
Cassan, D.J
1 results
1
Chan, A.H
1 results
1
Chen, T.
1 results
1
Chip-Hong Chang
1 results
1
Colonna, V.
1 results
1
Das, S.
1 results
1
Desgrez, S.
1 results
1
Dinh, A.
1 results
1
Eltawil, A.M
1 results
1
Engling Yeo
1 results
1
Gaggl, R.
1 results
1
Galal, S.
1 results
1
Ghoneima, M.
1 results
1
Hassan, H.
1 results
1
Hui Wu
1 results
1
Iizuka, K.
1 results
1
Jian Liang
1 results
1
Jong-Bum Park
1 results
1
Jose, A.P
1 results
1
Kappes, M.S
1 results
1
Klumperink, E.A.M
1 results
1
Lau, M.V
1 results
1
Leenaerts, D.M.W
1 results
1
Lin, A.C.Y
1 results
1
Lin, C.-C
1 results
1
Liu, T.-M
1 results
1
see all…
RESOURCE TYPE
Article
57 results
57
LANGUAGE
English
57 results
57
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