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ASIC design and synthesis RTL design using Verilog
Baskı/Yayın Bilgisi 2021Also available remotely for the University of the Philippines System via SpringerLink. Click here to access thru EZproxy
Available for University of the Philippines System via SpringerLink. Click here to access
Electronic Resource -
2
ASIC/SoC functional design verification a comprehensive guide to technologies and methodologies
Baskı/Yayın Bilgisi 2018Available for University of the Philippines System via SpringerLink. Click here to access
Also available remotely for University of the Philippines System via SpringerLink. Click here to access thru EZproxy
Electronic Resource -
3
PLD based design with VHDL RTL design, synthesis and implementation
Baskı/Yayın Bilgisi 2017Available for University of the Philippines Diliman via SpringerLink. Click here to access
Also available remotely for University of the Philippines Diliman via SpringerLink. Click here to access thru EZproxy
Electronic Resource -
4
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5
Logic design for array-based circuits a structured design methodology
Baskı/Yayın Bilgisi 1992Available for University of the Philippines System via ScienceDirect. Click here to access
Also available remotely for University of the Philippines System via ScienceDirect. Click here to access thru EZproxy
Electronic Resource -
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