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    Logic synthesis and SOC prototyping RTL design using VHDL av Taraate, Vaibbhav

    Publicerad 2020
    Available for University of the Philippines Diliman via SpringerLink. Click here to access
    Also available remotely for University of the Philippines Diliman via SpringerLink. Click here to access thru EZproxy
    Electronic Resource

    Logic synthesis and SOC prototyping RTL design using VHDL

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